公开(公告)号：US08898606B1

公开(公告)日：2014-11-25

申请号：US14080866

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rani Abou Ghaida ,  Ahmed Mohyeldin ,  Piyush Pathak ,  Swamy Muddu ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract translation: 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括：确定IC设计的布局的一部分，该部分包括连接多个设计连接的多条路线的第一模式; 基于所述多个路由确定所述多个设计连接的一个或多个集合; 以及由处理器确定基于所述一个或多个集合来连接所述部分内的所述多个设计连接的多条路线的第二模式。