公开(公告)号：US08739077B1

公开(公告)日：2014-05-27

申请号：US13782826

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Piyush Pathak ,  Piyush Verma ,  Sarah N. McGowan

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.

Abstract translation: 提供了用于修改用于制造半导体器件的电路的物理设计的方法以及用于制造集成电路的方法。 在一个实施例中，一种方法包括提供具有多个元件图案的电路设计布局。 提供了第一个有问题的图书馆。 确定电路设计布局内的初始电路部分和附加电路部分以匹配第一库中的有问题的部分，并且初始和附加电路部分具有重叠的外围边界。 提供了第二个更换部分库。 更换部分对应于有问题的部分。 与有问题的部分匹配的电路部分将替换为与各个有问题的部分对应的替换部分，以形成最终的电路布局。 更换部分的边界特性与由此更换的电路部分基本相同。

公开(公告)号：US08898606B1

公开(公告)日：2014-11-25

申请号：US14080866

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rani Abou Ghaida ,  Ahmed Mohyeldin ,  Piyush Pathak ,  Swamy Muddu ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract translation: 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括：确定IC设计的布局的一部分，该部分包括连接多个设计连接的多条路线的第一模式; 基于所述多个路由确定所述多个设计连接的一个或多个集合; 以及由处理器确定基于所述一个或多个集合来连接所述部分内的所述多个设计连接的多条路线的第二模式。

公开(公告)号：US10311186B2

公开(公告)日：2019-06-04

申请号：US15096551

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Piyush Pathak ,  Shobhit Malik ,  Uwe Paul Schroeder

IPC: G06F17/50

Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

公开(公告)号：US10055535B2

公开(公告)日：2018-08-21

申请号：US15277796

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Piyush Pathak ,  Robert C. Pack ,  Wei-Long Wang ,  Karthik Krishnamoorthy ,  Fadi S. Batarseh ,  Uwe Paul Schroeder ,  Sriram Madhavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.