公开(公告)号：US09583557B2

公开(公告)日：2017-02-28

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US20160064472A1

公开(公告)日：2016-03-03

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L49/02 ,  G06F17/50 ,  H01L21/02 ,  H01L23/522 ,  H01L21/822

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US10090258B1

公开(公告)日：2018-10-02

申请号：US15713843

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kevin Boyd ,  Robert Fox ,  Jeannine Trewhella ,  Roderick Alan Augur ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/535

Abstract: One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.