公开(公告)号：US10186524B2

公开(公告)日：2019-01-22

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US20180240885A1

公开(公告)日：2018-08-23

申请号：US15437846

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  Scott D. Luning ,  David Pritchard ,  Kasun Anupama Punchihewa

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

公开(公告)号：US10181522B2

公开(公告)日：2019-01-15

申请号：US15437846

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  Scott D. Luning ,  David Pritchard ,  Kasun Anupama Punchihewa

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

公开(公告)号：US09941301B1

公开(公告)日：2018-04-10

申请号：US15388772

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.