公开(公告)号：US10651136B2

公开(公告)日：2020-05-12

申请号：US15695391

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Francisco Ledesma Rabadan

IPC: H01L23/62 ,  H01L23/60 ,  H01L21/66 ,  G01R31/28 ,  H01L23/525

Abstract: When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.

公开(公告)号：US10347543B2

公开(公告)日：2019-07-09

申请号：US15810557

申请日：2017-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Rick Carter ,  Vikrant Chauhan ,  George Jonathan Kluth ,  Anurag Mittal ,  David Pritchard ,  Mahbub Rashed

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L27/12 ,  H01L29/49

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.

公开(公告)号：US20180240885A1

公开(公告)日：2018-08-23

申请号：US15437846

申请日：2017-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  Scott D. Luning ,  David Pritchard ,  Kasun Anupama Punchihewa

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/42356 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

公开(公告)号：US09666488B1

公开(公告)日：2017-05-30

申请号：US15095612

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  David Pritchard ,  Scott Luning ,  Guillaume Bouche ,  David Doman

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/285 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7838 ,  H01L29/7848

Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.

公开(公告)号：US10529704B1

公开(公告)日：2020-01-07

申请号：US16148323

申请日：2018-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Salvatore Cimino ,  David Pritchard ,  Lixia Lei ,  Heng Yang ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

公开(公告)号：US20190074257A1

公开(公告)日：2019-03-07

申请号：US15695391

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Francisco Ledesma Rabadan

IPC: H01L23/60 ,  H01L21/66 ,  H01L23/525 ,  G01R31/28

Abstract: When forming semiconductor devices, plasma-induced damage may be prevented or restricted by providing a conductive path between critical areas and the substrate of the semiconductor device. According to the present disclosure, a negative effect of any such protective structures on the performance of the semiconductor device may be significantly reduced by permanently interrupting the corresponding electrical connection at any appropriate point in time of the manufacturing sequence. Furthermore, respective fuse structures acting as current-sensitive areas may also be implemented in test structures in order to evaluate plasma-induced currents, thereby providing a possibility for a more efficient design of respective protective structures and/or for contributing to superior process control of critical plasma treatments.

公开(公告)号：US09465907B2

公开(公告)日：2016-10-11

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20160026748A1

公开(公告)日：2016-01-28

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案，将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US09224617B2

公开(公告)日：2015-12-29

申请号：US14167071

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Jason E. Stephens

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/02

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method is provided for fabricating cross-coupled line segments for use, for instance, as a hard mask in fabricating cross-coupled gates of two or more transistors. Fabricating the structure includes: providing a sacrificial mandrel on the substrate, the sacrificial mandrel including a transverse gap through the mandrel separating the sacrificial mandrel into a first mandrel portion and a second mandrel portion; providing a sidewall spacer along sidewalls of the sacrificial mandrel, where sidewall spacers along sidewalls of the first mandrel portion and the second mandrel portion merge within the transverse gap and form a crossbar; and removing the sacrificial mandrel and selectively cutting the sidewall spacers to define the cross-coupled line segments from the sidewall spacers and crossbar. The transverse gap may be provided by directly printing the first and second mandrel portions spaced apart, or by cutting the sacrificial mandrel to provide the gap.

Abstract translation: 提供了一种用于制造用于例如在制造两个或更多个晶体管的交叉耦合栅极中的硬掩模使用的交叉耦合线段的方法。 制造结构包括：在基底上提供牺牲心轴，所述牺牲心轴包括穿过所述心轴的横向间隙，将所述牺牲心轴分成第一心轴部分和第二心轴部分; 沿着所述牺牲心轴的侧壁提供侧壁间隔件，其中沿着所述第一心轴部分的侧壁和所述第二心轴部分的侧壁间隔在所述横向间隙内合并形成横杆; 并且移除牺牲心轴并选择性地切割侧壁间隔件以限定来自侧壁间隔件和横杆的交叉耦合线段。 横向间隙可以通过直接打印间隔开的第一和第二心轴部分，或者通过切割牺牲心轴来提供间隙来提供。

公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.