公开(公告)号：US20140339642A1

公开(公告)日：2014-11-20

申请号：US13896807

申请日：2013-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hsin-Neng TAI ,  Huey-Ming WANG

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/42364 ,  H01L29/66545

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract translation: 制造中的中间半导体结构包括基板。 多个栅极结构设置在衬底上，其中至少两个栅极结构由相邻栅极结构之间的牺牲材料隔开。 去除牺牲材料的一部分以在牺牲材料内形成开口，其中填充有具有高纵横比氧化物的填充材料。 去除多余的填充材料。 去除栅极结构的一部分以在栅极结构内形成栅极开口。 栅极开口填充有栅极盖材料，并且去除多余的栅极盖材料以形成覆盖栅极结构和牺牲材料的基本平坦的表面，以控制牺牲氧化物凹陷和栅极高度。

公开(公告)号：US20150048446A1

公开(公告)日：2015-02-19

申请号：US14505582

申请日：2014-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hsin-Neng TAI ,  Huey-Ming WANG

IPC: H01L29/423

CPC classification number: H01L29/4236 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/4232 ,  H01L29/42364 ,  H01L29/66545

Abstract: An intermediate semiconductor structure in fabrication includes a substrate. A plurality of gate structures is disposed over the substrate, with at least two of the gate structures separated by a sacrificial material between adjacent gate structures. A portion of the sacrificial material is removed to form openings within the sacrificial material, which are filled with a filler material having a high aspect ratio oxide. The excess filler material is removed. A portion of the gate structures is removed to form gate openings within the gate structures. The gate openings are filled with gate cap material and the excess gate cap material is removed to create a substantially planar surface overlaying the gate structures and the sacrificial material to control sacrificial oxide recess and gate height.

Abstract translation: 制造中的中间半导体结构包括基板。 多个栅极结构设置在衬底上，其中至少两个栅极结构由相邻栅极结构之间的牺牲材料隔开。 去除牺牲材料的一部分以在牺牲材料内形成开口，其中填充有具有高纵横比氧化物的填充材料。 去除多余的填充材料。 去除栅极结构的一部分以在栅极结构内形成栅极开口。 栅极开口填充有栅极盖材料，并且去除多余的栅极盖材料以形成覆盖栅极结构和牺牲材料的基本平坦的表面，以控制牺牲氧化物凹陷和栅极高度。

公开(公告)号：US20150270364A1

公开(公告)日：2015-09-24

申请号：US14730887

申请日：2015-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hung-Wei LIU ,  Rohit PAL ,  Hsin-Neng TAI ,  Huey-Ming WANG ,  Tae Hoon LEE ,  Songkram SRIVATHANAKUL ,  Danni CHEN

IPC: H01L29/423 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract translation: 提供了通过控制由这些方法形成的介电材料和半导体器件的凹陷来促进栅极高度均匀性的方法。 所述方法包括例如用n型晶体管和p型晶体管形成半导体器件的晶体管，n型晶体管和p型晶体管包括多个牺牲栅极结构和在上表面处的保护掩模 的多个牺牲栅极结构; 在多个牺牲栅极结构之上和之间提供电介质材料; 部分致密化介电材料以形成部分致密化的电介质材料; 进一步致密化部分致密化的介电材料以产生改性的介电材料; 以及在改性介电材料上形成基本平坦的表面，以控制电介质材料凹陷和栅极高度。

公开(公告)号：US20150087134A1

公开(公告)日：2015-03-26

申请号：US14032978

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hsin-Neng TAI ,  Puneet KHANNA ,  Zhenyu HU ,  Huey-Ming WANG

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate isolation region uniformity.

Abstract translation: 促进隔离区域均匀性的方法包括：图案化半导体衬底以在半导体衬底内形成至少一个隔离开口，该图案化包括至少部分地保留在半导体衬底的一部分上方的保护性硬掩模; 在所述至少一个隔离开口内和之上提供绝缘材料，以及对所述绝缘材料进行平坦化以便于制造所述半导体衬底内的隔离区域; 停止在保护性硬掩模上的平坦化，并将至少一部分保护性硬掩模暴露在半导体衬底的部分之上; 并且在所述至少一个隔离开口和所述暴露的所述半导体衬底的所述部分之上的所述暴露的保护性硬掩模之外，在所述至少一个隔离开口内留下所述绝缘材料的同时，将所述绝缘材料的剩余部分非选择性地去除， 半导体衬底，方便隔离区均匀。

公开(公告)号：US20150084131A1

公开(公告)日：2015-03-26

申请号：US14032740

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hung-Wei LIU ,  Rohit PAL ,  Hsin-Neng TAI ,  Huey-Ming WANG ,  Tae Hoon LEE ,  Songkram SRIVATHANAKUL ,  Danni CHEN

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42364 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.