公开(公告)号：US20160276336A1

公开(公告)日：2016-09-22

申请号：US14661202

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin LEE ,  Xiangxiang LU ,  Manjunatha PRABHU ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/7816 ,  H01L29/7835

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract translation: 提供了具有静电放电（ESD）保护和制造方法的高压半导体器件。 半导体器件包括在衬底上图案化的多个晶体管，该一个或多个公共栅极延伸穿过衬底的一部分，以及多个第一S / D触点和与公共栅极相关联的多个第二S / D触点 s）。 第二S / D触点设置在衬底内的多个载流子掺杂区域上。 一个或多个浮动节点设置在衬底上方，并且至少部分地设置在第二S / D触点之间，以有助于限定衬底内的多个载流子掺杂区域。 例如，载流子掺杂区域可以由具有公共载流子区域开口的掩模限定，浮动节点与公共载流子区域开口相交，并且有助于与公共开口一起限定多个分开的 载流子掺杂区域。

公开(公告)号：US20180342501A1

公开(公告)日：2018-11-29

申请号：US16055365

申请日：2018-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin LEE ,  Xiangxiang LU ,  Manjunatha PRABHU ,  Mahadeva Iyer NATARAJAN

IPC: H01L27/02 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/7816 ,  H01L29/7835

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.