公开(公告)号：US12124787B2

公开(公告)日：2024-10-22

申请号：US17519635

申请日：2021-11-05

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Shu Zhong ,  Ming Zhu ,  Pinghui Li ,  Yiang Aun Nga

IPC: G06F30/398 ,  G06F16/22

CPC classification number: G06F30/398 ,  G06F16/2282

Abstract: Disclosed are a system and method for automatically and systematically generating device-based design rules and corresponding device-based design rule checking (DRC) codes. In the system and method, design rules associated with specific devices are generated based on at least one table of related data (e.g., maturity status information, restriction status information, etc.) for different devices. Based on the design rules and on unique definitions for the specific devices, design rule checking (DRC) codes associated with the specific devices are generated. By using this approach, comprehensive and accurate device-based design rules and corresponding device-based DRC codes can be quickly generated to ensure acceptable product reliability and yield. Furthermore, processes used to generate the device-based DRC codes can be iteratively repeated (e.g., when the information used for generating the unique definitions of devices and/or generating the design rules changes) to update the device-based DRC codes and, thereby ensure DRC accuracy.

公开(公告)号：US11437406B2

公开(公告)日：2022-09-06

申请号：US16721955

申请日：2019-12-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Phyllis Shi Ya Lim ,  Handoko Linewih ,  Shu Zhong ,  Chor Shu Cheng

IPC: H01L29/94 ,  H01L27/12 ,  H01L29/40 ,  H01L29/78 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.

公开(公告)号：US20230144064A1

公开(公告)日：2023-05-11

申请号：US17519635

申请日：2021-11-05

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Shu Zhong ,  Ming Zhu ,  Pinghui Li ,  Yiang Aun Nga

IPC: G06F30/398 ,  G06F16/22

CPC classification number: G06F30/398 ,  G06F16/2282

Abstract: Disclosed are a system and method for automatically and systematically generating device-based design rules and corresponding device-based design rule checking (DRC) codes. In the system and method, design rules associated with specific devices are generated based on at least one table of related data (e.g., maturity status information, restriction status information, etc.) for different devices. Based on the design rules and on unique definitions for the specific devices, design rule checking (DRC) codes associated with the specific devices are generated. By using this approach, comprehensive and accurate device-based design rules and corresponding device-based DRC codes can be quickly generated to ensure acceptable product reliability and yield. Furthermore, processes used to generate the device-based DRC codes can be iteratively repeated (e.g., when the information used for generating the unique definitions of devices and/or generating the design rules changes) to update the device-based DRC codes and, thereby ensure DRC accuracy.