公开(公告)号：US20240194592A1

公开(公告)日：2024-06-13

申请号：US18064472

申请日：2022-12-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Mark D. Levy ,  Chung Foong Tan

IPC: H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L23/53271

Abstract: A fuse structure includes a fuse body including a polysilicon, and a metal heater over the fuse body. The fuse structure also includes a heating spreading structure thermally coupled to the metal heater and extending horizontally adjacent to at least one side of the fuse body. The metal heater can be a portion of a metal wire or a resistor including a resistive metal. The heat spreading structure may include a plurality of metal contacts.

公开(公告)号：US10985244B2

公开(公告)日：2021-04-20

申请号：US16451797

申请日：2019-06-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Shesh Mani Pandey ,  Chung Foong Tan ,  Baofu Zhu

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.

公开(公告)号：US20250006842A1

公开(公告)日：2025-01-02

申请号：US18345001

申请日：2023-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Pushparaj Dirgharaj Pathak ,  Chung Foong Tan

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.