公开(公告)号：US20220317393A1

公开(公告)日：2022-10-06

申请号：US17223059

申请日：2021-04-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： William J. Taylor, JR.

IPC: G02B6/42

Abstract: Disclosed is a chip structure that includes heater. The heater includes a heating element with a first end and a second end and, between the first and second ends, different portions with different cross-sectional areas. The heating element further includes first and second terminals at the first and second ends, respectively. Current flowing through the heating element between the first and second terminals causes the heating element to generate heat. However, due to the different cross-sectional areas of the different portions, the current densities through those different portions are different and, thus, the different portions of the heating element generate different amounts of heat per unit length. The heating element can be designed and placed on-chip to facilitate local thermal tuning of different regions of a device or of different devices without requiring multiple different heating elements within a relatively small chip area. Also disclosed is an associated method.

公开(公告)号：US20210240445A1

公开(公告)日：2021-08-05

申请号：US16776909

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Julien Frougier ,  Bipul C. Paul ,  William J. Taylor, JR.

IPC: G06F7/58 ,  G11C11/16

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

公开(公告)号：US20210399116A1

公开(公告)日：2021-12-23

申请号：US16907600

申请日：2020-06-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Alvin J. Joseph ,  William J. Taylor, JR. ,  Jeffrey B. Johnson

IPC: H01L29/68 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.