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Patent Agency Ranking
公开(公告)号：US11380993B2
公开(公告)日：2022-07-05
申请号：US16720279
申请日：2019-12-19
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Abdellatif Bellaouar
Abstract: Disclosed are embodiments of a transceiver front-end configured for a reduced noise figure (NF). Each of the embodiments includes an antenna, a transmitter branch and a receiver branch all connected to an input/output pad. The transmitter branch is coupled to the input/output pad (and thereby the antenna) by an impedance transformer. Only the receiver branch is selectively electrically connected to the input/output pad (and thereby the antenna) by a switch. A common matching network between the input/output pad and the switch provides both impedance matching and electrostatic discharge protection for the switch and the low noise amplifier, thereby reducing NF. Specific embodiments are disclosed for integration into specific technologies (e.g., fully depleted silicon-on-insulator (FDSOI) technology and fin-type field effect transistor (finFET) technology).
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公开(公告)号：US10942255B2
公开(公告)日：2021-03-09
申请号：US16157230
申请日：2018-10-11
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Arul Balasubramaniyan , Abdellatif Bellaouar
Abstract: The disclosure provides an apparatus including: a pair of signal injection transistors each having a gate terminal coupled to a differential reference signal, and a pair of cross-coupled amplifier transistors configured to amplify a voltage of the differential reference signal to yield a voltage-amplified reference signal at a local oscillator (LO) port of a mixer; an electronic oscillator having an oscillation output node coupled to the LO port of the mixer in parallel with the injection-locked buffer, and configured to generate an oscillator output for transmission to the output node based on a back gate bias voltage applied to the electronic oscillator; and an access transistor having a gate coupled to a switching node, and a back gate terminal coupled to the back gate bias voltage, wherein the access transistor is configured to enable or disable current flow through the electronic oscillator in parallel with the injection-locked buffer.
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公开(公告)号：US20210194125A1
公开(公告)日：2021-06-24
申请号：US16720279
申请日：2019-12-19
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Abdellatif Bellaouar
Abstract: Disclosed are embodiments of a transceiver front-end configured for a reduced noise figure (NF). Each of the embodiments includes an antenna, a transmitter branch and a receiver branch all connected to an input/output pad. The transmitter branch is coupled to the input/output pad (and thereby the antenna) by an impedance transformer. Only the receiver branch is selectively electrically connected to the input/output pad (and thereby the antenna) by a switch. A common matching network between the input/output pad and the switch provides both impedance matching and electrostatic discharge protection for the switch and the low noise amplifier, thereby reducing NF. Specific embodiments are disclosed for integration into specific technologies (e.g., fully depleted silicon-on-insulator (FDSOI) technology and fin-type field effect transistor (finFET) technology).
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公开(公告)号：US20250112602A1
公开(公告)日：2025-04-03
申请号：US18479139
申请日：2023-10-02
Applicant: GlobalFoundries U.S. Inc.
Inventor： Abdellatif Bellaouar , Shafiullah Syed
Abstract: A differential power amplifier circuit, including: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier, coupled in parallel with the first differential power amplifier, including a plurality of multi-gate transistors.
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公开(公告)号：US20250112598A1
公开(公告)日：2025-04-03
申请号：US18479205
申请日：2023-10-02
Applicant: GlobalFoundries U.S. Inc.
Inventor： Abdellatif Bellaouar , Shafiullah Syed
Abstract: A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.
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