公开(公告)号：US20240282853A1

公开(公告)日：2024-08-22

申请号：US18111995

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66704

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with workfunction metal in a drift region and methods of manufacture. The structure includes: a gate structure having at least a first workfunction metal in a channel region and a second workfunction metal, which is different from the first workfunction metal, in a trench in a drift region; and a sidewall spacer adjacent to the gate structure within the trench in the drift region.

公开(公告)号：US20240282847A1

公开(公告)日：2024-08-22

申请号：US18111959

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Sagar Premnath KARALKAR ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/74 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L29/66363

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; and a porous semiconductor region extending in the first well and the second well.

公开(公告)号：US20240304612A1

公开(公告)日：2024-09-12

申请号：US18118323

申请日：2023-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Sagar Premnath KARALKAR ,  Rajendran KRISHNASAMY ,  Anindya NATH

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and a deep trench isolation structure between the plurality of shallow trench isolation structures and extending into the semiconductor material deeper than the plurality of shallow trench isolation structures.

公开(公告)号：US20240030341A1

公开(公告)日：2024-01-25

申请号：US17872360

申请日：2022-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Rajendran KRISHNASAMY

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66704

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to laterally-diffused metal-oxide semiconductors and methods of manufacture. The structure includes: a drift region within a semiconductor substrate; a shallow trench isolation structure extending within the drift region; and a gate structure over the semiconductor substrate and extending within the shallow trench isolation structure.

公开(公告)号：US20230369474A1

公开(公告)日：2023-11-16

申请号：US17745280

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. HOLT ,  Shesh Mani PANDEY ,  Vibhor JAIN

IPC: H01L29/737 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.

公开(公告)号：US20230369473A1

公开(公告)日：2023-11-16

申请号：US17740725

申请日：2022-05-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Vibhor JAIN ,  Judson R. HOLT

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7371 ,  H01L29/66242 ,  H01L29/1004

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a subcollector under a buried insulator layer; a collector above the subcollector; a base within the buried insulator layer; an emitter above the base; and contacts to the subcollector, the base and the emitter.

公开(公告)号：US20230231041A1

公开(公告)日：2023-07-20

申请号：US17580127

申请日：2022-01-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Alexander M. DERRICKSON ,  Judson R. HOLT ,  Vibhor JAIN

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7371 ,  H01L29/66234 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/1004 ,  H01L29/41708

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.