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公开(公告)号:US10963780B2
公开(公告)日:2021-03-30
申请号:US15685672
申请日:2017-08-24
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam
IPC: G06N3/04 , G06N3/063 , G06F11/20 , G06F11/14 , H04L12/721 , H04L12/703 , H02J50/10 , H04L12/42
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
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公开(公告)号:US20210216853A1
公开(公告)日:2021-07-15
申请号:US17213871
申请日:2021-03-26
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam
IPC: G06N3/04 , G06N3/063 , G06F11/20 , G06F11/14 , H04L12/721 , H04L12/703
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
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公开(公告)号:US20180365553A1
公开(公告)日:2018-12-20
申请号:US15927367
申请日:2018-03-21
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam , Ravi Narayanaswami , Uday Kumar Dasari
Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
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公开(公告)号:US11948060B2
公开(公告)日:2024-04-02
申请号:US17570784
申请日:2022-01-07
Applicant: GOOGLE LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam , Ravi Narayanaswami , Uday Kumar Dasari
Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
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公开(公告)号:US11836598B2
公开(公告)日:2023-12-05
申请号:US17213871
申请日:2021-03-26
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam
IPC: G06N3/04 , G06F1/14 , G06N3/045 , G06N3/063 , G06F11/20 , G06F11/14 , H04L45/02 , H04L45/28 , H02J50/10 , H04L12/42
CPC classification number: G06N3/045 , G06F11/1423 , G06F11/2051 , G06N3/063 , H04L45/06 , H04L45/28 , H02J50/10 , H04L2012/421
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
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公开(公告)号:US12292473B2
公开(公告)日:2025-05-06
申请号:US18527902
申请日:2023-12-04
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam
IPC: G01R31/317 , G06N3/045 , H02J50/10 , H04L45/02 , H04L45/28
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
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公开(公告)号:US20240220773A1
公开(公告)日:2024-07-04
申请号:US18527902
申请日:2023-12-04
Applicant: Google LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam
CPC classification number: G06N3/045 , G06F11/1423 , G06F11/2051 , G06N3/063 , H04L45/06 , H04L45/28 , H02J50/10 , H04L2012/421
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.
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公开(公告)号:US20220147793A1
公开(公告)日:2022-05-12
申请号:US17570784
申请日:2022-01-07
Applicant: GOOGLE LLC
Inventor: Andreas Georg Nowatzyk , Olivier Temam , Ravi Narayanaswami , Uday Kumar Dasari
Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.
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