公开(公告)号：US12292473B2

公开(公告)日：2025-05-06

申请号：US18527902

申请日：2023-12-04

Applicant: Google LLC

Inventor： Andreas Georg Nowatzyk ,  Olivier Temam

IPC: G01R31/317 ,  G06N3/045 ,  H02J50/10 ,  H04L45/02 ,  H04L45/28

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

公开(公告)号：US20240220773A1

公开(公告)日：2024-07-04

申请号：US18527902

申请日：2023-12-04

Applicant: Google LLC

Inventor： Andreas Georg Nowatzyk ,  Olivier Temam

IPC: G06N3/045 ,  G06F11/14 ,  G06F11/20 ,  G06N3/063 ,  H02J50/10 ,  H04L12/42 ,  H04L45/02 ,  H04L45/28

CPC classification number: G06N3/045 ,  G06F11/1423 ,  G06F11/2051 ,  G06N3/063 ,  H04L45/06 ,  H04L45/28 ,  H02J50/10 ,  H04L2012/421

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

公开(公告)号：US20230162015A1

公开(公告)日：2023-05-25

申请号：US17985061

申请日：2022-11-10

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/063 ,  G06F13/00 ,  G06N3/045 ,  G06N3/048 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06N3/063 ,  G06F13/00 ,  G06N3/045 ,  G06N3/048 ,  G06F9/3887 ,  G06F9/3895 ,  G06F17/16

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

公开(公告)号：US20230004386A1

公开(公告)日：2023-01-05

申请号：US17892807

申请日：2022-08-22

Applicant: Google LLC

Inventor： Olivier Temam ,  Ravi Narayanaswami ,  Harshit Khaitan ,  Dong Hyuk Woo

IPC: G06F9/30 ,  G06F13/28 ,  G06N3/04 ,  G06N3/063 ,  G06F9/38

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

公开(公告)号：US11341402B2

公开(公告)日：2022-05-24

申请号：US16168135

申请日：2018-10-23

Applicant: Google LLC

Inventor： Pierre-Luc Cantin ,  Olivier Temam

IPC: G06N3/063 ,  G06N3/04

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.

公开(公告)号：US20220147793A1

公开(公告)日：2022-05-12

申请号：US17570784

申请日：2022-01-07

Applicant: GOOGLE LLC

Inventor： Andreas Georg Nowatzyk ,  Olivier Temam ,  Ravi Narayanaswami ,  Uday Kumar Dasari

IPC: G06N3/04 ,  H04B1/16 ,  G06N3/063

Abstract: A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.

公开(公告)号：US10706007B2

公开(公告)日：2020-07-07

申请号：US16129663

申请日：2018-09-12

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06N3/08

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

公开(公告)号：US20190205756A1

公开(公告)日：2019-07-04

申请号：US16297091

申请日：2019-03-08

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/08 ,  G06N20/00 ,  G06F8/41 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N20/00 ,  G06T1/20

Abstract: Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.

公开(公告)号：US20180341479A1

公开(公告)日：2018-11-29

申请号：US15903991

申请日：2018-02-23

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06F9/30 ,  G06F9/34 ,  G06F17/16 ,  G06F9/32

Abstract: Methods, systems, and apparatus, including an apparatus for accessing a N-dimensional tensor, the apparatus including, for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, and a number of iterations of a loop for the dimension. The apparatus includes a hardware adder and a processor. The processor obtains an instruction to access a particular element of the N-dimensional tensor. The N-dimensional tensor has multiple elements arranged across each of the N dimensions, where N is an integer that is equal to or greater than one. The processor determines, using the partial address offset value elements and the hardware adder, an address of the particular element and outputs data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US10127494B1

公开(公告)日：2018-11-13

申请号：US15667230

申请日：2017-08-02

Applicant: GOOGLE LLC

Inventor： Pierre-luc Cantin ,  Olivier Temam

IPC: G06N3/063 ,  G06N3/04

Abstract: A circuit for performing neural network computations for a neural network is described. The circuit includes plurality of neural network layers each including a crossbar arrays. The plurality of crossbar arrays are formed in a common substrate in a stacked configuration. Each crossbar array includes a set of crosspoint devices. A respective electrical property of each of the crosspoint devices is adjustable to represent a weight value that is stored for each respective crosspoint device. A processing unit is configured to adjust the respective electrical properties of each of the crosspoint devices by pre-loading each of the crosspoint devices with a tuning signal. A value of the turning signal for each crosspoint device is a function of the weight value represented by each respective crosspoint device.