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    Multi-partition memory sharing with multiple components
    1.
    发明授权
    Multi-partition memory sharing with multiple components 有权

    公开(公告)号：US12013780B2

    公开(公告)日：2024-06-18

    申请号：US17425918

    申请日：2020-08-19

    Applicant: Google LLC

    Inventor： Suyog Gupta ,  Ravi Narayanaswami ,  Uday Kumar Dasari ,  Ali Iranli ,  Pavan Thirunagari ,  Vinu Vijay Kumar ,  Sunitha R. Kosireddy

    IPC: G06F12/0802 ,  G06F3/06

    CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0679 ,  G06F2212/60

    Abstract: Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components. The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.

    APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES
    2.
    发明申请
    APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES 审中-公开

    公开(公告)号：US20190156187A1

    公开(公告)日：2019-05-23

    申请号：US15819753

    申请日：2017-11-21

    Applicant: Google LLC

    Inventor： Uday Kumar Dasari ,  Olivier Temam ,  Ravi Narayanaswami ,  Dong Hyuk Woo

    IPC: G06N3/063 ,  G06N3/04

    Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

    APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES
    4.
    发明申请
    APPARATUS AND MECHANISM FOR PROCESSING NEURAL NETWORK TASKS USING A SINGLE CHIP PACKAGE WITH MULTIPLE IDENTICAL DIES 有权

    公开(公告)号：US20210256361A1

    公开(公告)日：2021-08-19

    申请号：US17186598

    申请日：2021-02-26

    Applicant: Google LLC

    Inventor： Uday Kumar Dasari ,  Olivier Temam ,  Ravi Narayanaswami ,  Dong Hyuk Woo

    IPC: G06N3/063 ,  G06N3/04 ,  G06F15/78

    Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

    Memory Sharing
    5.
    发明申请
    Memory Sharing 有权

    公开(公告)号：US20220300421A1

    公开(公告)日：2022-09-22

    申请号：US17425918

    申请日：2020-08-19

    Applicant: Google LLC

    Inventor： Suyog Gupta ,  Ravi Narayanaswami ,  Uday Kumar Dasari ,  Ali Iranli ,  Pavan Thirunagari ,  Vinu Vijay Kumar ,  Sunitha R. Kosireddy

    IPC: G06F12/0802 ,  G06F3/06

    Abstract: Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components. The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.

    HARDWARE CIRCUIT FOR ACCELERATING NEURAL NETWORK COMPUTATIONS
    7.
    发明申请
    HARDWARE CIRCUIT FOR ACCELERATING NEURAL NETWORK COMPUTATIONS 有权

    公开(公告)号：US20210326683A1

    公开(公告)日：2021-10-21

    申请号：US16973087

    申请日：2019-12-19

    Applicant: Google LLC

    Inventor： Ravi Narayanaswami ,  Dong Hyuk Woo ,  Suyog Gupta ,  Uday Kumar Dasari

    IPC: G06N3/063 ,  G06N3/04

    Abstract: Methods, systems, and apparatus, including computer-readable media, are described for a hardware circuit configured to implement a neural network. The circuit includes multiple super tiles. Each super tile includes a unified memory for storing inputs to a neural network layer and weights for the layer. Each super tile includes multiple compute tiles. Each compute tile executes a compute thread that is used to perform the computations to generate an output for the neural network layer. Each super tile includes arbitration logic coupled to the unified memory and each compute tile. The arbitration logic is configured to: pass inputs stored in the unified memory to the compute tiles; pass weights stored in the unified memory to the compute tiles; and pass, to the unified memory, the output generated for the layer based on computations performed at the compute tiles using the inputs and the weights for the layer.

    Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies
    10.
    发明授权
    Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies 有权

    公开(公告)号：US10936942B2

    公开(公告)日：2021-03-02

    申请号：US15819753

    申请日：2017-11-21

    Applicant: Google LLC

    Inventor： Uday Kumar Dasari ,  Olivier Temam ,  Ravi Narayanaswami ,  Dong Hyuk Woo

    IPC: G06N3/063 ,  G06N3/04 ,  G06F15/78

    Abstract: Apparatus and methods for processing neural network models are provided. The apparatus can comprise a plurality of identical artificial intelligence processing dies. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies can include at least one inter-die input block and at least one inter-die output block. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies is communicatively coupled to another artificial intelligence processing die among the plurality of identical artificial intelligence processing dies by way of one or more communication paths from the at least one inter-die output block of the artificial intelligence processing die to the at least one inter-die input block of the artificial intelligence processing die. Each artificial intelligence processing die among the plurality of identical artificial intelligence processing dies corresponds to at least one layer of a neural network.

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