Optimizing hardware FIFO instructions

    公开(公告)号:US10733016B1

    公开(公告)日:2020-08-04

    申请号:US16395697

    申请日:2019-04-26

    申请人: Google LLC

    摘要: Methods, systems, and apparatus for scheduling first-in-first-out instructions are described. In one aspect, a method includes receiving data representing code of a program to be executed by a processing unit comprising hardware processors. For each of one or more of the hardware processors, an order of independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor is identified in the data representing the code of the program. For each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions is determined. A new order of the independent groups of FIFO instructions for execution by the hardware processor is generated based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor.

    Propagating reduced-precision on computation graphs

    公开(公告)号:US11972238B2

    公开(公告)日:2024-04-30

    申请号:US17838710

    申请日:2022-06-13

    申请人: Google LLC

    发明人: Yuanzhong Xu

    IPC分类号: G06F8/41 G06F16/901 G06N20/00

    摘要: Methods, systems, and apparatus for propagating reduced-precision on computation graphs are described. In one aspect, a method includes receiving data specifying a directed graph that includes operators for a program. The operators include first operators that each represent a numerical operation performed on numerical values having a first level of precision and second operators that each represent a numerical operation performed on numerical values having a second level of precision. One or more downstream operators are identified for a first operator. A determination is made whether each downstream operator represents a numerical operation that is performed on input values having the second level of precision. Whenever each downstream operator represents a numerical operation that is performed on input values having the second level of precision, a precision of numerical values output by the operation represented by the first operator is adjusted to the second level of precision.

    Optimizing hardware FIFO instructions

    公开(公告)号:US11221879B2

    公开(公告)日:2022-01-11

    申请号:US16919968

    申请日:2020-07-02

    申请人: Google LLC

    摘要: Methods, systems, and apparatus for scheduling first-in-first-out instructions are described. In one aspect, a method includes receiving data representing code of a program to be executed by a processing unit comprising hardware processors. For each of one or more of the hardware processors, an order of independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor is identified in the data representing the code of the program. For each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions is determined. A new order of the independent groups of FIFO instructions for execution by the hardware processor is generated based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor.

    PROPAGATING REDUCED-PRECISION ON COMPUTATION GRAPHS

    公开(公告)号:US20200249924A1

    公开(公告)日:2020-08-06

    申请号:US16263730

    申请日:2019-01-31

    申请人: Google LLC

    发明人: Yuanzhong Xu

    IPC分类号: G06F8/41 G06N20/00 G06F16/901

    摘要: Methods, systems, and apparatus for propagating reduced-precision on computation graphs are described. In one aspect, a method includes receiving data specifying a directed graph that includes operators for a program. The operators include first operators that each represent a numerical operation performed on numerical values having a first level of precision and second operators that each represent a numerical operation performed on numerical values having a second level of precision. One or more downstream operators are identified for a first operator. A determination is made whether each downstream operator represents a numerical operation that is performed on input values having the second level of precision. Whenever each downstream operator represents a numerical operation that is performed on input values having the second level of precision, a precision of numerical values output by the operation represented by the first operator is adjusted to the second level of precision.

    Vector-Quantized Image Modeling
    6.
    发明公开

    公开(公告)号:US20240112088A1

    公开(公告)日:2024-04-04

    申请号:US18520083

    申请日:2023-11-27

    申请人: Google LLC

    IPC分类号: G06N20/00

    CPC分类号: G06N20/00

    摘要: Systems and methods are provided for vector-quantized image modeling using vision transformers and improved codebook handling. In particular, the present disclosure provides a Vector-quantized Image Modeling (VIM) approach that involves pretraining a machine learning model (e.g., Transformer model) to predict rasterized image tokens autoregressively. The discrete image tokens can be encoded from a learned Vision-Transformer-based VQGAN (example implementations of which can be referred to as ViT-VQGAN). The present disclosure proposes multiple improvements over vanilla VQGAN from architecture to codebook learning, yielding better efficiency and reconstruction fidelity. The improved ViT-VQGAN further improves vector-quantized image modeling tasks, including unconditional image generation, conditioned image generation (e.g., class-conditioned image generation), and unsupervised representation learning.

    Propagating reduced-precision on computation graphs

    公开(公告)号:US11385875B2

    公开(公告)日:2022-07-12

    申请号:US16263730

    申请日:2019-01-31

    申请人: Google LLC

    发明人: Yuanzhong Xu

    IPC分类号: G06F8/41 G06F16/901 G06N20/00

    摘要: Methods, systems, and apparatus for propagating reduced-precision on computation graphs are described. In one aspect, a method includes receiving data specifying a directed graph that includes operators for a program. The operators include first operators that each represent a numerical operation performed on numerical values having a first level of precision and second operators that each represent a numerical operation performed on numerical values having a second level of precision. One or more downstream operators are identified for a first operator. A determination is made whether each downstream operator represents a numerical operation that is performed on input values having the second level of precision. Whenever each downstream operator represents a numerical operation that is performed on input values having the second level of precision, a precision of numerical values output by the operation represented by the first operator is adjusted to the second level of precision.

    OPTIMIZING HARDWARE FIFO INSTRUCTIONS
    9.
    发明申请

    公开(公告)号:US20200341807A1

    公开(公告)日:2020-10-29

    申请号:US16919968

    申请日:2020-07-02

    申请人: Google LLC

    IPC分类号: G06F9/48 G06F9/38

    摘要: Methods, systems, and apparatus for scheduling first-in-first-out instructions are described. In one aspect, a method includes receiving data representing code of a program to be executed by a processing unit comprising hardware processors. For each of one or more of the hardware processors, an order of independent groups of first-in-first-out (FIFO) instructions for execution by the hardware processor is identified in the data representing the code of the program. For each independent group of FIFO instructions for execution by the hardware processor, a path length metric that represents how long it will take to reach an end of the program from the independent group of FIFO instructions is determined. A new order of the independent groups of FIFO instructions for execution by the hardware processor is generated based at least on the path length metric for each independent group of FIFO instructions for execution by the hardware processor.