专利检索 ap:("GSI Technology, Inc.") AND inv:"Jae-Hyeong Kim" 第 1 页

1.

发明申请
SYSTEMS AND METHODS INVOLVING LOCK-LOOP CIRCUITS, CLOCK SIGNAL ALIGNMENT, PHASE-AVERAGING FEEDBACK CLOCK CIRCUITRY 审中-公开

公开(公告)号：US20180109248A1

公开(公告)日：2018-04-19

申请号：US15845578

申请日：2017-12-18

申请人： GSI Technology, Inc.

发明人： Yu-Chi Cheng , Patrick Chuang , Jae-Hyeong Kim

IPC分类号： H03K5/15 , H03L7/081

摘要： Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

2.

发明授权
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry 有权

公开(公告)号：US09853633B1

公开(公告)日：2017-12-26

申请号：US15188907

申请日：2016-06-21

申请人： GSI Technology, Inc.

发明人： Yu-Chi Cheng , Patrick Chuang , Jae-Hyeong Kim

IPC分类号： H03L7/06 , H03K5/15 , H03L7/081

CPC分类号： H03K5/1506 , H03K5/135 , H03K2005/00052 , H03L7/08 , H03L7/0812 , H03L7/16

摘要： Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

3.

发明授权
Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry 有权

公开(公告)号：US10425070B2

公开(公告)日：2019-09-24

申请号：US15845578

申请日：2017-12-18

申请人： GSI Technology, Inc.

发明人： Yu-Chi Cheng , Patrick Chuang , Jae-Hyeong Kim

IPC分类号： H03K5/15 , H03L7/081 , H03K5/135 , H03L7/08 , H03L7/16 , H03K5/00

摘要： Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

4.

发明授权
Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features 有权

公开(公告)号：US09935635B2

公开(公告)日：2018-04-03

申请号：US15248985

申请日：2016-08-26

申请人： GSI Technology, Inc.

发明人： Jae-Hyeong Kim , Chih Tseng , Patrick Chuang

IPC分类号： H03K3/00 , H03K19/0185

CPC分类号： H03K19/0185

摘要： A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.