公开(公告)号：US11139373B2

公开(公告)日：2021-10-05

申请号：US16688008

申请日：2019-11-19

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40 ,  H01L29/778

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

公开(公告)号：US10218346B1

公开(公告)日：2019-02-26

申请号：US15704458

申请日：2017-09-14

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Greg P. Klowak ,  Xiaodong Cui

IPC: H01L29/20 ,  H01L23/522 ,  H01L29/778 ,  H03K17/081 ,  H01L29/205 ,  H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L23/31

Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

公开(公告)号：US10529802B2

公开(公告)日：2020-01-07

申请号：US15988453

申请日：2018-05-24

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.