公开(公告)号：US10529802B2

公开(公告)日：2020-01-07

申请号：US15988453

申请日：2018-05-24

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

公开(公告)号：US12027449B2

公开(公告)日：2024-07-02

申请号：US17974794

申请日：2022-10-27

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward Macrobbie

IPC: H01L29/417 ,  H01L23/482 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861

CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L29/8611

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US11527460B2

公开(公告)日：2022-12-13

申请号：US17085137

申请日：2020-10-30

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward MacRobbie

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20 ,  H01L29/861 ,  H01L29/417

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US11139373B2

公开(公告)日：2021-10-05

申请号：US16688008

申请日：2019-11-19

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40 ,  H01L29/778

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.