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    Suite of tools to design integrated circuits
    3.
    发明授权
    Suite of tools to design integrated circuits 失效
    套件设计集成电路的工具

    公开(公告)号：US07430725B2

    公开(公告)日：2008-09-30

    申请号：US11156319

    申请日：2005-06-18

    申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

    发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

    摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

    Dynamically-tunable memory controller
    4.
    发明授权
    Dynamically-tunable memory controller 失效
    动态可调内存控制器

    公开(公告)号：US06453434B2

    公开(公告)日：2002-09-17

    申请号：US09938161

    申请日：2001-08-23

    申请人： Gary Scott Delp ,  Gary Paul McClannahan

    发明人： Gary Scott Delp ,  Gary Paul McClannahan

    IPC分类号： G11C2900

    CPC分类号： G06F13/1694

    摘要： A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

    摘要翻译： 存储器控制器电路布置和方法利用调节电路，该调谐电路动态地控制存储器控制操作的定时，而不是简单地依赖于在存储器控制器启动时硬连线或初始化的固定定时参数。 对存储器控制操作的定时的动态控制通常结合存储器测试控制逻辑，其使用动态选择的给定定时参数的值来验证存储器存储设备是否可靠地运行。 然后，基于这种测试的结果，选择性地更新和重新测试这样的动态选择的值，直到找到最优值。 动态选择的值可以用于设置一个或多个可编程寄存器，每个可编程寄存器可以依次用于控制可编程延迟计数器的操作，该可编程延迟计数器使得状态机逻辑电路中的状态转变能够启动存储器的性能 由逻辑电路进行控制操作。 动态调谐还可以利用唯一的二进制搜索引擎电路装置，其基于使用该平均值执行的测试的结果，以两个寄存器之一的平均值存储在这些寄存器中的当前值。 通过选择性地更新这种寄存器，以最小的电路发生快速收敛到最佳值。

    Dynamically-tunable memory controller
    5.
    发明授权
    Dynamically-tunable memory controller 失效
    动态可调内存控制器

    公开(公告)号：US06334174B1

    公开(公告)日：2001-12-25

    申请号：US09247501

    申请日：1999-02-10

    申请人： Gary Scott Delp ,  Gary Paul McClannahan

    发明人： Gary Scott Delp ,  Gary Paul McClannahan

    IPC分类号： G06F1200

    CPC分类号： G06F13/1694

    摘要： A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

    摘要翻译： 存储器控制器电路布置和方法利用调节电路，该调谐电路动态地控制存储器控制操作的定时，而不是简单地依赖于在存储器控制器启动时硬连线或初始化的固定定时参数。 对存储器控制操作的定时的动态控制通常结合存储器测试控制逻辑，其使用动态选择的给定定时参数的值来验证存储器存储设备是否可靠地运行。 然后，基于这种测试的结果，选择性地更新和重新测试这样的动态选择的值，直到找到最优值。 动态选择的值可以用于设置一个或多个可编程寄存器，每个可编程寄存器可以依次用于控制可编程延迟计数器的操作，该可编程延迟计数器使得状态机逻辑电路中的状态转变能够启动存储器的性能 由逻辑电路进行控制操作。 动态调谐还可以利用唯一的二进制搜索引擎电路装置，其基于使用该平均值执行的测试的结果，以两个寄存器之一的平均值存储在这些寄存器中的当前值。 通过选择性地更新这种寄存器，以最小的电路发生快速收敛到最佳值。

    Simplified process to design integrated circuits
    6.
    发明授权
    Simplified process to design integrated circuits 有权
    集成电路设计简化过程

    公开(公告)号：US07055113B2

    公开(公告)日：2006-05-30

    申请号：US10335360

    申请日：2002-12-31

    申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

    发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

    摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

    Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags
    7.
    发明授权
    Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags 失效
    在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置

    公开(公告)号：US06289430B1

    公开(公告)日：2001-09-11

    申请号：US09251029

    申请日：1999-02-18

    申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Chad B. McBride ,  Gary Paul McClannahan

    发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Chad B. McBride ,  Gary Paul McClannahan

    IPC分类号： G06F1210

    CPC分类号： G06F12/0875 ,  G06F12/0292

    摘要： A method and apparatus are provided for target addressing and translation in a non-uniform memory environment with user defined target tags. The apparatus for target addressing and translation includes a processor and a first address translation unit coupled to the processor. The first address translation unit translates an effective address (EA) to a real address (RA). The first address translation unit includes a target tag associated with each address translation. A second address translation unit translates a real address (RA) to a target address (TA). The second address translation unit includes a target tag associated with each address translation. A cache includes a cache directory and a target tag is stored into the cache directory with each cache fill.

    摘要翻译： 提供了一种用于在具有用户定义的目标标签的非均匀存储环境中进行目标寻址和转换的方法和装置。 用于目标寻址和转换的装置包括耦合到处理器的处理器和第一地址转换单元。 第一地址翻译单元将有效地址（EA）转换为实际地址（RA）。 第一地址转换单元包括与每个地址转换相关联的目标标签。 第二地址转换单元将实际地址（RA）转换为目标地址（TA）。 第二地址转换单元包括与每个地址转换相关联的目标标签。 高速缓存包括缓存目录，并且目标标签被存储到每个缓存填充的高速缓存目录中。

    Method and apparatus for direct memory access (DMA) with dataflow blocking for users
    8.
    发明授权
    Method and apparatus for direct memory access (DMA) with dataflow blocking for users 失效
    用于直接存储器访问（DMA）的方法和装置，具有用户的数据流阻塞

    公开(公告)号：US06453366B1

    公开(公告)日：2002-09-17

    申请号：US09251043

    申请日：1999-02-18

    申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Chad B. McBride ,  Gary Paul McClannahan

    发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Chad B. McBride ,  Gary Paul McClannahan

    IPC分类号： G06F1328

    CPC分类号： G06F13/28

    摘要： A method and apparatus are provided for implementing direct memory access (DMA) with dataflow blocking for users for processing data communications in a communications system. A DMA starting address register receives an initial DMA starting address and a DMA length register receives an initial DMA length. A DMA state machine receives a control input for starting the DMA. The DMA state machine updates the DMA starting address to provide a current DMA starting address. The DMA state machine loads a DMA ending address. A DMA blocking logic receives the current DMA starting address and the DMA ending address and blocks received memory requests only within a current active DMA region.

    摘要翻译： 提供了一种用于实现具有用于处理通信系统中的数据通信的用户的数据流阻塞的直接存储器访问（DMA）的方法和装置。 DMA起始地址寄存器接收初始DMA起始地址，DMA长度寄存器接收初始DMA长度。 DMA状态机接收用于启动DMA的控制输入。 DMA状态机更新DMA起始地址以提供当前的DMA起始地址。 DMA状态机加载DMA结束地址。 DMA阻塞逻辑接收当前DMA起始地址和DMA结束地址，并仅在当前活动DMA区域内阻止接收到的存储器请求。

    Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device
    9.
    发明授权
    Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device 有权
    具有可编程延迟计数器的存储器控​​制器，用于基于受控存储器件的时序参数进行调谐性能

    公开(公告)号：US06438670B1

    公开(公告)日：2002-08-20

    申请号：US09166004

    申请日：1998-10-02

    申请人： Gary Paul McClannahan

    发明人： Gary Paul McClannahan

    IPC分类号： G06F1200

    CPC分类号： G06F13/1694

    摘要： A memory controller circuit arrangement and method utilize a tuning circuit that controls the timing of memory control operations via one or more programmable delay counters. Each counter is programmed to cycle a selected number of clock cycles to delay performance of a memory control operation to meet a predetermined timing parameter for a memory storage device coupled to the controller. Through the use of programmable delay counters, a variety of memory storage devices having varying timing parameters may be supported by the same memory controller design. Moreover, the use of programmable delay counters permit a single path of execution in a memory controller state machine to support any number of timing parameter variations for a particular timing characteristic, as well as multiple timing characteristics.

    摘要翻译： 存储器控制器电路布置和方法利用调谐电路，其经由一个或多个可编程延迟计数器来控制存储器控制操作的定时。 每个计数器被编程为循环选定数量的时钟周期以延迟存储器控制操作的性能，以满足耦合到控制器的存储器存储设备的预定时序参数。 通过使用可编程延迟计数器，可以通过相同的存储器控​​制器设计支持具有变化的定时参数的各种存储器存储设备。 此外，使用可编程延迟计数器允许存储器控制器状态机中的单个执行路径支持特定定时特性以及多个定时特性的任何数量的定时参数变化。