公开(公告)号：US20090179680A1

公开(公告)日：2009-07-16

申请号：US12014172

申请日：2008-01-15

申请人： Paul Gary Reuland ,  Brian Andrew Schuelke

发明人： Paul Gary Reuland ,  Brian Andrew Schuelke

IPC分类号： G06F1/04 ,  G06F17/50

CPC分类号： H03K5/1502 ,  G06F1/10

摘要： A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

摘要翻译： 一种在具有在电压和温度的多个工作点处工作的电压岛的专用集成电路（ASIC）上实现平衡时钟分配网络的方法和装置，以及提供主题电路所在的设计结构。 时钟源耦合到提供时钟信号的N电平平衡时钟树。 多个电压岛中的每一个包括相应的电压移位器和接收时钟信号的可编程延迟功能。 每个相应的电压移位器和可编程延迟功能为相关电压岛的相应的平衡时钟树提供第二时钟信号。 系统控制器为每个相应的电压移位器和可编程延迟功能提供相应的控制输入。 相应的控制输入根据各个电压岛的操作模式动态变化。

公开(公告)号：US06728818B2

公开(公告)日：2004-04-27

申请号：US09894428

申请日：2001-06-27

申请人： Brian Eric Bakke ,  Robert Edward Galbraith ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Paul Gary Reuland ,  Timothy Jerry Schimke

发明人： Brian Eric Bakke ,  Robert Edward Galbraith ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Paul Gary Reuland ,  Timothy Jerry Schimke

IPC分类号： G06F1310

CPC分类号： G06F11/201 ,  G06F11/2005 ,  G06F11/2007

摘要： An Input/Output (I/O) adapter for use with a second I/O adapter in a clustered configuration. The I/O adapter includes a dedicated communication link, such as a high-speed serial bus, that provides for communication between the I/O adapter and the second I/O adapter. The I/O adapter also includes a message passing circuit, coupled to the dedicated communication link, that allows for transferring of data between the I/O adapter and the second I/O adapter. The I/O adapter further includes a doorbell circuit, coupled to the message passing circuit, that generates interrupts to provide a low level communication between the I/O adapter and the second I/O adapter. A mirroring directory, coupled to the message passing circuit, is also included in the I/O adapter to provide for the mirroring of cache directory writes.

摘要翻译： 用于集群配置中的第二个I / O适配器的输入/输出（I / O）适配器。 I / O适配器包括专用通信链路，例如高速串行总线，其提供I / O适配器和第二I / O适配器之间的通信。 I / O适配器还包括耦合到专用通信链路的消息传递电路，其允许在I / O适配器和第二I / O适配器之间传送数据。 I / O适配器还包括耦合到消息传递电路的门铃电路，其生成中断以在I / O适配器和第二I / O适配器之间提供低级通信。 耦合到消息传递电路的镜像目录也包含在I / O适配器中，以提供缓存目录写入的镜像。

公开(公告)号：US07055113B2

公开(公告)日：2006-05-30

申请号：US10335360

申请日：2002-12-31

申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US06530003B2

公开(公告)日：2003-03-04

申请号：US09916022

申请日：2001-07-26

申请人： Brian Eric Bakke ,  Carl Edward Forhan ,  Robert Edward Galbraith ,  Jessica Gisi ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Douglas David Prigge ,  Paul Gary Reuland ,  Timothy Jerry Schimke

发明人： Brian Eric Bakke ,  Carl Edward Forhan ,  Robert Edward Galbraith ,  Jessica Gisi ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Douglas David Prigge ,  Paul Gary Reuland ,  Timothy Jerry Schimke

IPC分类号： G06F1120

CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F12/0802 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A method for maintaining data coherency in a dual Input/Output(I/O) adapter having primary and secondary adapters, wherein each of the primary and secondary adapters includes resident write cache data and directory storage devices. The method includes utilizing a split point to separate each of the cache data and directory storage devices into first and second regions, wherein the first regions contain the primary adapter cache data and directory information and the second regions contain the secondary adapter cache data and directory information. Information stored in the primary adapter cache data and directory storage devices is mirrored into the secondary adapter cache data and directory storage devices or, alternatively, information stored in the secondary adapter cache data and directory storage devices is mirrored into the primary adapter cache data and directory storage devices utilizing a dedicated communication link, such as a high-speed serial bus, between the primary and secondary adapters.

摘要翻译： 一种用于在具有主适配器和辅助适配器的双输入/输出（I / O）适配器中维护数据一致性的方法，其中主适配器和次适配器中的每一个包括驻留写入高速缓存数据和目录存储设备。 该方法包括利用分割点将高速缓存数据和目录存储设备中的每一个分离成第一和第二区域，其中第一区域包含主适配器高速缓存数据和目录信息，并且第二区域包含次适配器高速缓存数据和目录信息 。 存储在主适配器高速缓存数据和目录存储设备中的信息被镜像到辅适配器高速缓存数据和目录存储设备中，或者，存储在辅适配器高速缓存中的数据和目录存储设备的信息被镜像到主适配器高速缓存数据和目录 在主适配器和次适配器之间使用诸如高速串行总线的专用通信链路的存储设备。

公开(公告)号：US07430725B2

公开(公告)日：2008-09-30

申请号：US11156319

申请日：2005-06-18

申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US07069523B2

公开(公告)日：2006-06-27

申请号：US10318623

申请日：2002-12-13

申请人： George Wayne Nation ,  Gary Scott Delp ,  Paul Gary Reuland

发明人： George Wayne Nation ,  Gary Scott Delp ,  Paul Gary Reuland

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/64

摘要： A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

摘要翻译： 用于设计集成电路的工具，可优化电路内存储块的位置和时序。 给定已经扩散和逻辑整合的多个块的制造片，这里的存储器生成工具自动考虑片的可用扩散存储器和门阵列，以将其配置和优化成客户对存储器的要求。 存储器生成工具具有存储器管理器，存储器资源数据库，存储器资源选择器和存储器编程器。 这些都一起进行交互以从存储器资源数据库内的可用存储器生成存储器。 内存作曲家实际上为存储器生成RTL逻辑外壳，并以Verilog，VHDL或其他工具合成语言输出内存设计。 一旦创建内存，就会进行测试。 成功测试后，内存管理员更新内存资源数据库，以指示成功测试的内存不再可用作生成更多内存的资源。 设计集成商可以检查存储器设计输出，并将存储器，其定时，测试等与集成电路的其他块和功能进一步集成。

公开(公告)号：US6154791A

公开(公告)日：2000-11-28

申请号：US871945

申请日：1997-06-10

申请人： Christopher John Kimble ,  Thomas J. Osten ,  Paul Gary Reuland ,  Daniel Guy Young

发明人： Christopher John Kimble ,  Thomas J. Osten ,  Paul Gary Reuland ,  Daniel Guy Young

IPC分类号： G06F11/20 ,  G06F11/30

CPC分类号： G06F11/201

摘要： A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit. Besides being serially connected to form a single communication path, the loop resiliency circuits can be divided into groups wherein the loop resiliency circuits in each group are serially connected to form a communication path. Separate loop resiliency circuits then selectively connect these communication paths to a main communication path including an initiator. As a further alternative, a second initiator can be selectively placed in one of the communication paths via another loop resiliency circuit.

摘要翻译： 用于DASD阵列的通信系统包括多个环路回弹电路和多个选择电路。 DASD阵列包括多个DASD槽。 每个DASD插槽可以接收DASD，并且每个DASD从调节器接收电力。 环路弹性电路形成至少第一通信路径。 每个回路弹性电路与DASD时隙中的一个相关联，并且基于选择信号选择性地包括第一通信路径中的相关联的DASD时隙。 多个选择电路也与DASD时隙中的一个相关联; 因此也与多个环路回弹电路中的一个相关联。 每个选择电路连接到相关联的DASD插槽，并在相关联的DASD插槽中接收来自稳压器的输出。 基于调节器输出或其缺乏，选择电路产生用于相关联的回路弹性电路的选择信号。 除了串联连接以形成单个通信路径之外，环路弹性电路可以被划分成组，其中每组中的环路弹性电路串联连接以形成通信路径。 然后，单独的回路弹性电路选择性地将这些通信路径连接到包括启动器的主通信路径。 作为另一替代方案，可以经由另一回路弹性电路将第二启动器选择性地置于通信路径之一中。

公开(公告)号：US06684266B2

公开(公告)日：2004-01-27

申请号：US09810645

申请日：2001-03-16

申请人： Troy Evan Faber ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Paul Gary Reuland ,  Timothy Jerry Schimke ,  Russell Paul VanDuine ,  Bruce Marshall Walk ,  Todd Jason Youngman

发明人： Troy Evan Faber ,  Frederic Lawrence Huss ,  Daniel Frank Moertl ,  Paul Gary Reuland ,  Timothy Jerry Schimke ,  Russell Paul VanDuine ,  Bruce Marshall Walk ,  Todd Jason Youngman

IPC分类号： G06F300

CPC分类号： H04B1/74

摘要： A storage area network (SAN) fibre channel arbitrated loop (FCAL) multiple system, multiple resource, storage enclosure and a method are provided for performing enclosure maintenance concurrent with device operations. The storage enclosure includes a plurality of storage resources or storage devices, a plurality of IO adapters (IOAs) coupled to the storage area network and a pair of enclosure services node cards. Each enclosure services node card includes loop connections for the plurality of storage resources. Each enclosure services node card includes a respective global bus connection and a loop connection to each of the plurality of IOAs. Each enclosure services node card is used concurrently by the multiple systems to manage the plurality of storage resources. In the method for performing enclosure maintenance concurrent with device operations, identical maintenance procedures are implemented for the enclosure services node cards and the storage devices. The enclosure services node cards are removable cards and contain active components including port bypass circuits (PBCs). Fibre channel (FC) connections for the plurality of storage resources provide redundant paths to each storage resource and allows access to data on the storage resources to continue when one of the pair of enclosure services node cards fails or is being maintained. Out of band communications to the enclosure services node cards are provided with the global buses, such as I2C buses, rather than FC loop. Multiple IOAs can concurrently use the same enclosure services node card without contention or collision.

摘要翻译： 提供存储区域网络（SAN）光纤通道仲裁环路（FCAL）多系统，多资源，存储机柜和方法，用于与设备操作并发执行机箱维护。 存储机箱包括多个存储资源或存储设备，耦合到存储区域网络的多个IO适配器（IOA）和一对机箱服务节点卡。 每个机箱服务节点卡包括用于多个存储资源的循环连接。 每个机箱服务节点卡包括相应的全局总线连接和到多个IOA中的每一个的环路连接。 每个机箱服务节点卡由多个系统同时使用来管理多个存储资源。 在与设备操作并发执行机箱维护的方法中，对于机箱服务节点卡和存储设备实施相同的维护过程。 机箱服务节点卡是可移动卡，包含有源组件，包括端口旁路电路（PBC）。 用于多个存储资源的光纤通道（FC）连接为每个存储资源提供冗余路径，并允许对存储资源上的数据进行访问，以在一对机箱服务节点卡中的一个失败或正在维护时继续。 与机箱的带外通信服务节点卡提供有全局总线，例如I2C总线，而不是FC循环。 多个IOA可以同时使用相同的机箱服务节点卡，而不会发生争用或冲突。

公开(公告)号：US07551002B1

公开(公告)日：2009-06-23

申请号：US12014172

申请日：2008-01-15

申请人： Paul Gary Reuland ,  Brian Andrew Schuelke

发明人： Paul Gary Reuland ,  Brian Andrew Schuelke

IPC分类号： H03K19/00

CPC分类号： H03K5/1502 ,  G06F1/10

摘要： A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

摘要翻译： 一种在具有在电压和温度的多个工作点处工作的电压岛的专用集成电路（ASIC）上实现平衡时钟分配网络的方法和装置，以及提供主题电路所在的设计结构。 时钟源耦合到提供时钟信号的N电平平衡时钟树。 多个电压岛中的每一个包括相应的电压移位器和接收时钟信号的可编程延迟功能。 每个相应的电压移位器和可编程延迟功能为相关电压岛的相应的平衡时钟树提供第二时钟信号。 系统控制器为每个相应的电压移位器和可编程延迟功能提供相应的控制输入。 相应的控制输入根据各个电压岛的操作模式动态变化。

公开(公告)号：US06959428B2

公开(公告)日：2005-10-25

申请号：US10465186

申请日：2003-06-19

申请人： Robert Neal Carlton Broberg, III ,  Troy Evan Faber ,  Gary Scott Delp ,  Paul Gary Reuland ,  Daniel James Murray

发明人： Robert Neal Carlton Broberg, III ,  Troy Evan Faber ,  Gary Scott Delp ,  Paul Gary Reuland ,  Daniel James Murray

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters. The register address generation tool may be used with a suite of generation tools to achieve the rapid design and realization of a new semiconductor product.

摘要翻译： 在半导体产品的设计中使用寄存器地址生成工具。 对于可在总线上寻址的寄存器和/或存储器，寄存器地址生成工具创建互连RTL，头文件，静态时序分析约束文件和验证测试用例。 该工具还在设计中保持半导体产品设计中所产生的内容和可用资源之间的一致性。 如果没有使用任何寄存器和/或存储器，则寄存器地址生成工具可以进一步产生将将这些未使用的资源转换成诸如控制寄存器，状态寄存器等的性能增强特征的RTL。寄存器地址生成 工具读取具有应用集的设计数据库，以确定什么硬件和什么晶体管结构可用。 它还接收总线规范和地址参数作为输入。 寄存器地址生成工具可以与一套生成工具一起使用，以实现新的半导体产品的快速设计和实现。