公开(公告)号：US06453434B2

公开(公告)日：2002-09-17

申请号：US09938161

申请日：2001-08-23

申请人： Gary Scott Delp ,  Gary Paul McClannahan

发明人： Gary Scott Delp ,  Gary Paul McClannahan

IPC分类号： G11C2900

CPC分类号： G06F13/1694

摘要： A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

摘要翻译： 存储器控制器电路布置和方法利用调节电路，该调谐电路动态地控制存储器控制操作的定时，而不是简单地依赖于在存储器控制器启动时硬连线或初始化的固定定时参数。 对存储器控制操作的定时的动态控制通常结合存储器测试控制逻辑，其使用动态选择的给定定时参数的值来验证存储器存储设备是否可靠地运行。 然后，基于这种测试的结果，选择性地更新和重新测试这样的动态选择的值，直到找到最优值。 动态选择的值可以用于设置一个或多个可编程寄存器，每个可编程寄存器可以依次用于控制可编程延迟计数器的操作，该可编程延迟计数器使得状态机逻辑电路中的状态转变能够启动存储器的性能 由逻辑电路进行控制操作。 动态调谐还可以利用唯一的二进制搜索引擎电路装置，其基于使用该平均值执行的测试的结果，以两个寄存器之一的平均值存储在这些寄存器中的当前值。 通过选择性地更新这种寄存器，以最小的电路发生快速收敛到最佳值。

公开(公告)号：US06334174B1

公开(公告)日：2001-12-25

申请号：US09247501

申请日：1999-02-10

申请人： Gary Scott Delp ,  Gary Paul McClannahan

发明人： Gary Scott Delp ,  Gary Paul McClannahan

IPC分类号： G06F1200

CPC分类号： G06F13/1694

摘要： A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

摘要翻译： 存储器控制器电路布置和方法利用调节电路，该调谐电路动态地控制存储器控制操作的定时，而不是简单地依赖于在存储器控制器启动时硬连线或初始化的固定定时参数。 对存储器控制操作的定时的动态控制通常结合存储器测试控制逻辑，其使用动态选择的给定定时参数的值来验证存储器存储设备是否可靠地运行。 然后，基于这种测试的结果，选择性地更新和重新测试这样的动态选择的值，直到找到最优值。 动态选择的值可以用于设置一个或多个可编程寄存器，每个可编程寄存器可以依次用于控制可编程延迟计数器的操作，该可编程延迟计数器使得状态机逻辑电路中的状态转变能够启动存储器的性能 由逻辑电路进行控制操作。 动态调谐还可以利用唯一的二进制搜索引擎电路装置，其基于使用该平均值执行的测试的结果，以两个寄存器之一的平均值存储在这些寄存器中的当前值。 通过选择性地更新这种寄存器，以最小的电路发生快速收敛到最佳值。

公开(公告)号：US07430725B2

公开(公告)日：2008-09-30

申请号：US11156319

申请日：2005-06-18

申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US06765911B1

公开(公告)日：2004-07-20

申请号：US09243858

申请日：1999-02-03

申请人： Mark William Branstad ,  Jonathan William Byrn ,  Gary Scott Delp ,  Philip Lynn Leichty ,  Todd Edwin Leonard ,  Gary Paul McClannahan ,  John Emery Nordman ,  Kevin Gerard Plotz ,  John Handley Shaffer ,  Albert Alfonse Slane

发明人： Mark William Branstad ,  Jonathan William Byrn ,  Gary Scott Delp ,  Philip Lynn Leichty ,  Todd Edwin Leonard ,  Gary Paul McClannahan ,  John Emery Nordman ,  Kevin Gerard Plotz ,  John Handley Shaffer ,  Albert Alfonse Slane

IPC分类号： H04L1256

CPC分类号： H04L47/58 ,  H04L12/5601 ,  H04L47/50 ,  H04L2012/5652 ,  H04L2012/5679

摘要： A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

摘要翻译： 提供了一种用于在通信网络中实现通信的方法和装置。 用于实现通信的装置包括到通信网络的系统接口。 调度器调度入队单元和要发送的入队帧。 分段器将帧和小区划分成应用于媒体适配块的小区或帧，以在多个模式中选择的一个模式中进行传输。

公开(公告)号：US06498782B1

公开(公告)日：2002-12-24

申请号：US09243956

申请日：1999-02-03

申请人： Mark William Branstad ,  Jonathan William Byrn ,  Gary Scott Delp ,  Philip Lynn Leichty ,  Todd Edwin Leonard ,  Gary Paul McClannahan ,  John Emery Nordman ,  Kevin Gerard Plotz ,  John Handley Shaffer ,  Albert Alfonse Slane

发明人： Mark William Branstad ,  Jonathan William Byrn ,  Gary Scott Delp ,  Philip Lynn Leichty ,  Todd Edwin Leonard ,  Gary Paul McClannahan ,  John Emery Nordman ,  Kevin Gerard Plotz ,  John Handley Shaffer ,  Albert Alfonse Slane

IPC分类号： G06F1100

CPC分类号： H04L47/24 ,  H04L12/40032 ,  H04L12/4015 ,  H04L12/413 ,  H04L47/10 ,  H04L47/22 ,  H04L47/50 ,  H04L47/568 ,  H04L47/6215

摘要： A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

摘要翻译： 提供了一种用于实现通信网络中的通信的方法和千兆以太网通信适配器。 定义要发送的数据的传输队列。 为传输队列设置传输速率。 要发送的数据在传输队列中排队。 传输队列可以被划分为多个优先级队列，例如使用时轮，并为每个传输队列设置一个传输速率。

公开(公告)号：US07055113B2

公开(公告)日：2006-05-30

申请号：US10335360

申请日：2002-12-31

申请人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

发明人： Robert Neal Carlton Broberg, III ,  Jonathan William Byrn ,  Gary Scott Delp ,  Michael K. Eneboe ,  Gary Paul McClannahan ,  George Wayne Nation ,  Paul Gary Reuland ,  Thomas Sandoval ,  Matthew Scott Wingren

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.

摘要翻译： 本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。 输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。 输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。 切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。 这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。 这些设计经过其他工具的合格，测试和验证。 这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。 该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。 这些工具也具有迭代模式和全局模式。 在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。 在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。 这套生成工具生成设计视图，包括用于制造铸造的合格网表。

公开(公告)号：US20120175683A1

公开(公告)日：2012-07-12

申请号：US13424747

申请日：2012-03-20

申请人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

发明人： Ramnath Venkatraman ,  Michael N. Dillon ,  David A. Gardner ,  Carl Anthony Monzel, III ,  Subramanian Ramesh ,  Robert C. Armstrong ,  Gary Scott Delp ,  Scott Allen Peterson

IPC分类号： H01L27/105

CPC分类号： H03K19/1735 ,  G06F2217/64 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807

摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

摘要翻译： 提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。 通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。 电路架构可以实现单个单元或多个单元内的晶体管的互连。 互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。 此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。 通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

公开(公告)号：US07831653B2

公开(公告)日：2010-11-09

申请号：US10318792

申请日：2002-12-13

申请人： George Wayne Nation ,  Gary Scott Delp ,  William D. Scharf ,  Narayanan Raman ,  John N. Fryar, III ,  Majid Bemanian

发明人： George Wayne Nation ,  Gary Scott Delp ,  William D. Scharf ,  Narayanan Raman ,  John N. Fryar, III ,  Majid Bemanian

IPC分类号： G06F15/16

CPC分类号： H04L69/12

摘要： A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

摘要翻译： 包括片和多个壳的部分制造的半导体芯片是用于通信和网络芯片的模板。 该片具有多个I / O端口，块和PHY。 硬件PHY被建立为对应于高速数据传输协议。 模板的内部包括逻辑门阵列和可配置存储器。 一旦选择了数据接收和传输的特定协议，逻辑门阵列和可配置存储器可以被编程，否则被配置为开发用于数据联网和通信的协议层。

公开(公告)号：US06959428B2

公开(公告)日：2005-10-25

申请号：US10465186

申请日：2003-06-19

申请人： Robert Neal Carlton Broberg, III ,  Troy Evan Faber ,  Gary Scott Delp ,  Paul Gary Reuland ,  Daniel James Murray

发明人： Robert Neal Carlton Broberg, III ,  Troy Evan Faber ,  Gary Scott Delp ,  Paul Gary Reuland ,  Daniel James Murray

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters. The register address generation tool may be used with a suite of generation tools to achieve the rapid design and realization of a new semiconductor product.

摘要翻译： 在半导体产品的设计中使用寄存器地址生成工具。 对于可在总线上寻址的寄存器和/或存储器，寄存器地址生成工具创建互连RTL，头文件，静态时序分析约束文件和验证测试用例。 该工具还在设计中保持半导体产品设计中所产生的内容和可用资源之间的一致性。 如果没有使用任何寄存器和/或存储器，则寄存器地址生成工具可以进一步产生将将这些未使用的资源转换成诸如控制寄存器，状态寄存器等的性能增强特征的RTL。寄存器地址生成 工具读取具有应用集的设计数据库，以确定什么硬件和什么晶体管结构可用。 它还接收总线规范和地址参数作为输入。 寄存器地址生成工具可以与一套生成工具一起使用，以实现新的半导体产品的快速设计和实现。

公开(公告)号：US5758087A

公开(公告)日：1998-05-26

申请号：US664131

申请日：1996-06-14

申请人： Kenneth Dale Aaker ,  Gary Scott Delp ,  Brad Louis Brech

发明人： Kenneth Dale Aaker ,  Gary Scott Delp ,  Brad Louis Brech

IPC分类号： G06F13/00 ,  G06F9/46 ,  G06F12/00 ,  G06F17/30 ,  H04L29/06 ,  G06F9/06

CPC分类号： H04L67/42

摘要： A method and apparatus are provided for generation of predicted responses in a computer communications network system. A server in the computer communications network system predicts the client's next request based on the present client's request. The server sets a trigger that recognizes a match of the client's predicted request. When a client's predicted request arrives, the trigger sends the response. Additionally, the server associates a timeout action with the predicted response so that if a predicted request is not received within the timeout interval or other events occur before the predicted request arrives, the triggered response is removed and an alternative action is performed.

摘要翻译： 提供了一种用于在计算机通信网络系统中产生预测响应的方法和装置。 计算机通信网络系统中的服务器基于当前客户端的请求预测客户端的下一个请求。 服务器设置一个触发器，用于识别客户端预测请求的匹配。 当客户端的预测请求到达时，触发器发送响应。 另外，服务器将超时动作与预测的响应相关联，使得如果在超时间隔内未接收到预测请求或在预测请求到达之前发生其他事件，则触发的响应被移除，并执行替代动作。