公开(公告)号：US20170294434A1

公开(公告)日：2017-10-12

申请号：US15333868

申请日：2016-10-25

Applicant: General Electric Company

Inventor： Avinash Srikrishnan KASHYAP ,  Peter Micah SANDVIK ,  James Jay MCMAHON ,  Ljubisa Dragoljub STEVANOVIC

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/16

CPC classification number: H01L27/0617 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.