公开(公告)号：US10299744B2

公开(公告)日：2019-05-28

申请号：US15354760

申请日：2016-11-17

申请人： General Electric Company ,  Teledyne DALSA, Inc. ,  Teledyne DALSA B.V.

发明人： Biju Jacob ,  Brian David Yanoff ,  William Andrew Hennessy ,  Jeffery Jon Shaw ,  Douglas Albagli ,  Bartholomeus G. M. H. Dillen ,  Inge Peters ,  Anton Van Arendonk

IPC分类号： A61B6/00 ,  H01L27/146 ,  G01T1/20 ,  G01T7/00

摘要： An x-ray detector comprises: a housing, including a cover removably fastened on a flange of a flanged base and forming a semi-hermetic seal therebetween, the flanged base including a bottom surface and the flange surrounding a perimeter of the bottom surface; and an x-ray imager positioned on the bottom surface, the x-ray imager including a scintillator and an image sensor, wherein the seal semi-hermetically encloses the x-ray imager in the housing, and is positioned nonadjacently to surfaces in contact with the x-ray imager. In this way, a simpler and less costly seal for a digital x-ray panel can be provide; furthermore, the seal is reusable and resealable, facilitating repair and refurbishment of the device.

公开(公告)号：US10283557B2

公开(公告)日：2019-05-07

申请号：US14985785

申请日：2015-12-31

申请人： General Electric Company

发明人： Biju Jacob ,  Habib Vafi ,  Brian David Yanoff ,  Jeffery Jon Shaw ,  Jianjun Guo

IPC分类号： H01L27/00 ,  H01L27/146 ,  G01T1/20 ,  G01T1/24

摘要： Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.

公开(公告)号：US20180132804A1

公开(公告)日：2018-05-17

申请号：US15354760

申请日：2016-11-17

申请人： General Electric Company ,  Teledyne DALSA, Inc. ,  Teledyne DALSA B.V.

发明人： Biju Jacob ,  Brian David Yanoff ,  William Andrew Hennessy ,  Jeffery Jon Shaw ,  Douglas Albagli ,  Bartholomeus G.M.H. Dillen ,  Inge Peters ,  Anton Van Arendonk

IPC分类号： A61B6/00 ,  H01L27/146

CPC分类号： A61B6/4208 ,  G01T1/2018 ,  G01T7/00 ,  H01L27/14634 ,  H01L27/14663

摘要： An x-ray detector comprises: a housing, including a cover removably fastened on a flange of a flanged base and forming a semi-hermetic seal therebetween, the flanged base including a bottom surface and the flange surrounding a perimeter of the bottom surface; and an x-ray imager positioned on the bottom surface, the x-ray imager including a scintillator and an image sensor, wherein the seal semi-hermetically encloses the x-ray imager in the housing, and is positioned nonadjacently to surfaces in contact with the x-ray imager. In this way, a simpler and less costly seal for a digital x-ray panel can be provide; furthermore, the seal is reusable and resealable, facilitating repair and refurbishment of the device.

公开(公告)号：US10686003B2

公开(公告)日：2020-06-16

申请号：US14985739

申请日：2015-12-31

申请人： General Electric Company

发明人： Biju Jacob ,  Habib Vafi ,  Brian David Yanoff ,  Jeffery Jon Shaw ,  Jianjun Guo

IPC分类号： G01T1/24 ,  H01L27/146 ,  H04N5/378

摘要： Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.

公开(公告)号：US20170194375A1

公开(公告)日：2017-07-06

申请号：US14985785

申请日：2015-12-31

申请人： General Electric Company

发明人： Biju Jacob ,  Habib Vafi ,  Brian David Yanoff ,  Jeffery Jon Shaw ,  Jianjun Guo

IPC分类号： H01L27/146 ,  G01T1/24 ,  G01T1/20

CPC分类号： H01L27/14689 ,  G01T1/2018 ,  G01T1/247 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14658 ,  H01L27/14661 ,  H01L27/14663 ,  H01L27/1469

摘要： Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.

公开(公告)号：US20170194374A1

公开(公告)日：2017-07-06

申请号：US14985739

申请日：2015-12-31

申请人： General Electric Company

发明人： Biju Jacob ,  Habib Vafi ,  Brian David Yanoff ,  Jeffery Jon Shaw ,  Jianjun Guo

IPC分类号： H01L27/146 ,  G01T1/24 ,  H04N5/378

摘要： Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.