公开(公告)号：US06545980B1

公开(公告)日：2003-04-08

申请号：US09171238

申请日：1998-12-15

Applicant: Geoffrey Dive ,  Werner Beisel

Inventor： Geoffrey Dive ,  Werner Beisel

IPC: G01R3108

CPC classification number: H04J3/08 ,  H04J3/12 ,  H04J3/14 ,  H04J2203/0051 ,  H04J2203/0057

Abstract: A synchronous transmission system is disclosed in which the transmission paths (leased lines) extend over several individual transmission systems (Sx). Monitoring devices (NIM) with access to at least one byte of the control data area are provided in synchronous transmission systems to write data into or read data out of the control data area. The monitoring devices (NIM) may thus be controlled and monitored by a signal source (S1).

Abstract translation: 公开了一种同步传输系统，其中传输路径（租用线路）在几个单独的传输系统（Sx）上延伸。 在同步传输系统中提供具有访问控制数据区域的至少一个字节的监控设备（NIM），以将数据写入或从控制数据区域读出数据。 监控设备（NIM）因此可以被信号源（S1）控制和监视。

公开(公告)号：US06188685B1

公开(公告)日：2001-02-13

申请号：US08766767

申请日：1996-12-03

Applicant: Michael Wolf ,  Geoffrey Dive ,  Jürgen Kasper

Inventor： Michael Wolf ,  Geoffrey Dive ,  Jürgen Kasper

IPC: H04L1250

CPC classification number: H04J3/0623

Abstract: A transmission system is indicated for digital signals combined into a multiplex signal, and a network element for such a transmission system. Each network element contains an adapter circuit to balance phase variations in an incoming multiplex signal. The adapter circuit has a buffer memory (1) for payload data bytes, a write address generator (2) which controls the buffer memory (1) in a way so that a number of payload data bytes is stored within one write cycle, and has a read address generator (3) which controls the buffer memory (1) in a way so that the number of payload data bytes stored within the write cycle is greater than the number of payload data bytes read during the read cycle. Each network element has a sort facility (5) which sorts the read payload data bytes, so that a multiplex signal that is transmitted by a network element has the established frame format.

Abstract translation: 指示用于组合成多路复用信号的数字信号的传输系统和用于这种传输系统的网络元件。 每个网络元件都包含适配器电路，以平衡输入复用信号中的相位变化。 适配器电路具有用于有效载荷数据字节的缓冲存储器（1），写入地址生成器（2），其以一定量的有效载荷数据字节存储在一个写入周期中的方式控制缓冲存储器（1），并且具有 读取地址生成器（3），其以使得在写入周期内存储的有效载荷数据字节的数量大于在读取周期期间读取的有效载荷数据字节的数量的方式来控制缓冲存储器（1）。 每个网络元件具有对读取的有效载荷数据字节进行排序的分类设施（5），使得由网络元件发送的多路复用信号具有建立的帧格式。

公开(公告)号：US06526069B1

公开(公告)日：2003-02-25

申请号：US09244628

申请日：1999-02-04

Applicant: Michael Wolf ,  Geoffrey Dive

Inventor： Michael Wolf ,  Geoffrey Dive

IPC: H04J306

CPC classification number: H04J3/0623 ,  H04J3/076 ,  H04J2203/0094 ,  Y10S370/906 ,  Y10S370/907 ,  Y10S370/916

Abstract: A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a digital input signal. The synchronization device includes a receiver unit for receiving the input signal, a packet assembly device for packaging the input signal into subassemblies of the transport modules, a buffer memory, a writer for writing data bits of the input signal out of the subassemblies into the buffer memory with a write clock, a reader, for reading data bits out of the buffer memory with a read clock in order to form the output signal, and a sending unit (SO) for sending synchronous output signals. The effective bit rate of the subassemblies compared to the standardized value is either lowered or raised by selecting the write clock lower than the read clock.

Abstract translation: 一种用于同步数字消息传输系统的同步装置，其产生包括从数字输入信号与帧时钟同步的连续传输模块的同步输出信号。 同步装置包括用于接收输入信号的接收器单元，用于将输入信号封装到传输模块的子组件中的分组组装装置，缓冲存储器，写入器，用于将输入信号的数据位从子组件写入缓冲器 具有写入时钟的存储器，读取器，用于以读取时钟从缓冲存储器读出数据位以形成输出信号;以及发送单元（SO），用于发送同步输出信号。 通过选择低于读时钟的写时钟，子组件与标准化值相比的有效位速率降低或升高。

公开(公告)号：US06836851B2

公开(公告)日：2004-12-28

申请号：US09810250

申请日：2001-03-19

Applicant: Geoffrey Dive

Inventor： Geoffrey Dive

IPC: G06F112

CPC classification number: H04J3/0691 ,  G06F1/12 ,  H04L7/0008 ,  H04Q11/0478

Abstract: The present invention relates to a method for the synchronization of a first and a least one second module, each having a clock generator. The invention furthermore relates to such modules, a master program module, a slave program module and a device for this purpose. It is proposed that the first module, transmits a first clock signal generated by its clock generator to the second module, which synchronizes its clock generator with the first clock signal. The second module transmits a second clock signal generated by its clock generator that is synchronized with the first clock signal to the first module, which determines a time difference value between the first clock signal and the second clock signal, which time difference value is essentially due the transmission time of the first and the second clock signal between the first and the second module. The first module transmits an item of information about the (first) time difference value to the second module, which adjusts its clock generator on the basis of said information.

Abstract translation: 本发明涉及一种用于同步第一和至少一个第二模块的方法，每个模块具有时钟发生器。 本发明还涉及这样的模块，主程序模块，从属程序模块和用于此目的的设备。 提出第一模块将由其时钟发生器产生的第一时钟信号发送到第二模块，该第二模块将其时钟发生器与第一时钟信号同步。 第二模块将由其时钟发生器产生的与第一时钟信号同步的第二时钟信号发送到第一模块，该第一模块确定第一时钟信号和第二时钟信号之间的时间差值，该时间差值基本上是由于 第一和第二时钟信号在第一和第二模块之间的传输时间。 第一模块将关于（第一）时间差值的信息项发送到第二模块，该第二模块基于所述信息调整其时钟发生器。