Frequency Domain Approach for Efficient Computation of Fixed-point Equalization Targets
    1.
    发明申请
    Frequency Domain Approach for Efficient Computation of Fixed-point Equalization Targets 有权
    用于有效计算定点均衡目标的频域方法

    公开(公告)号:US20090161245A1

    公开(公告)日:2009-06-25

    申请号:US12273265

    申请日:2008-11-18

    IPC分类号: G11B5/035

    摘要: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

    摘要翻译: 本发明的各种实施例提供了用于均衡输入信号的系统和方法。 例如,本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。 这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。 将初始值作为目标值提供给均衡器电路,并且至少部分地基于初始值和滤波器系数来计算总体目标。 基于总体目标计算更新的值,并且将更新的值作为目标值提供给均衡器电路。

    Frequency domain approach for efficient computation of fixed-point equalization targets
    2.
    发明授权
    Frequency domain approach for efficient computation of fixed-point equalization targets 有权
    用于有效计算定点均衡目标的频域方法

    公开(公告)号:US07924523B2

    公开(公告)日:2011-04-12

    申请号:US12273265

    申请日:2008-11-18

    IPC分类号: G11B5/035

    摘要: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

    摘要翻译: 本发明的各种实施例提供了用于均衡输入信号的系统和方法。 例如,本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。 这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。 将初始值作为目标值提供给均衡器电路,并且至少部分地基于初始值和滤波器系数来计算总体目标。 基于总体目标计算更新的值,并且将更新的值作为目标值提供给均衡器电路。

    Systems and methods for equalizer optimization in a storage access retry
    4.
    发明授权
    Systems and methods for equalizer optimization in a storage access retry 有权
    存储访问重试中均衡器优化的系统和方法

    公开(公告)号:US07948699B2

    公开(公告)日:2011-05-24

    申请号:US12348236

    申请日:2009-01-02

    IPC分类号: G11B5/09

    摘要: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.

    摘要翻译: 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。

    Systems and Methods for Equalizer Optimization in a Storage Access Retry
    5.
    发明申请
    Systems and Methods for Equalizer Optimization in a Storage Access Retry 有权
    存储访问重试中均衡器优化的系统和方法

    公开(公告)号:US20100172046A1

    公开(公告)日:2010-07-08

    申请号:US12348236

    申请日:2009-01-02

    IPC分类号: G11B20/10

    摘要: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.

    摘要翻译: 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。

    Systems and methods for format efficient calibration for servo data based harmonics calculation
    6.
    发明授权
    Systems and methods for format efficient calibration for servo data based harmonics calculation 失效
    基于伺服数据的谐波计算格式有效校准的系统和方法

    公开(公告)号:US08300349B2

    公开(公告)日:2012-10-30

    申请号:US12851425

    申请日:2010-08-05

    IPC分类号: G11B21/02 G11B5/09

    摘要: Various embodiments of the present invention provide systems and methods for servo data based harmonics calculation. For example, a method for calculating harmonics is disclosed that includes: providing a data processing circuit; receiving a first data set derived from a data source during a servo data processing period; performing a first harmonics calculation using the first data set to yield a first harmonics ratio; receiving a second data set derived from a source other than the previously mentioned data source during a user data processing period; performing a second harmonics calculation using the second data set to yield a second harmonics ratio; and calculating a ratio of the first harmonics ratio to the second harmonics ratio.

    摘要翻译: 本发明的各种实施例提供了用于基于伺服数据的谐波计算的系统和方法。 例如,公开了一种用于计算谐波的方法,包括:提供数据处理电路; 在伺服数据处理期间接收从数据源导出的第一数据组; 使用所述第一数据组执行第一谐波计算以产生第一谐波比; 在用户数据处理期间接收从除了前述数据源之外的源得到的第二数据集; 使用所述第二数据组执行二次谐波计算以产生第二谐波比; 以及计算所述第一谐波比与所述第二谐波比的比率。

    Systems and methods for adaptive CBD estimation in a storage device
    7.
    发明授权
    Systems and methods for adaptive CBD estimation in a storage device 有权
    存储设备中自适应CBD估计的系统和方法

    公开(公告)号:US08154818B2

    公开(公告)日:2012-04-10

    申请号:US12663345

    申请日:2008-10-20

    IPC分类号: G11B21/02

    CPC分类号: G11B5/6029

    摘要: Various embodiments of the present invention provide systems and methods for adaptive channel bit density estimation. For example, various embodiments of the present invention provide methods for adaptively estimating channel bit density. Such methods include providing a storage medium (178) that includes information corresponding to a process data set, and accessing the process data set from the storage medium (505). A first channel bit density estimate (535) is computed based at least in part on a first portion of the process data set (520-530), and a second channel bit density estimate (535) is calculated based at least in part on the first portion of the process data set, a second portion of the process data set (520-530) and the first channel bit density estimate (535).

    摘要翻译: 本发明的各种实施例提供了用于自适应信道比特密度估计的系统和方法。 例如,本发明的各种实施例提供了自适应地估计信道比特密度的方法。 这样的方法包括提供包括与过程数据集相对应的信息的存储介质(178),以及从存储介质(505)访问过程数据集。 至少部分地基于过程数据集(520-530)的第一部分来计算第一信道比特密度估计(535),并且至少部分地基于所述第二信道比特密度估计 过程数据集的第一部分,过程数据集(520-530)的第二部分和第一信道比特密度估计(535)。

    DIBIT EXTRACTION FOR ESTIMATION OF CHANNEL PARAMETERS
    8.
    发明申请
    DIBIT EXTRACTION FOR ESTIMATION OF CHANNEL PARAMETERS 有权
    用于估计通道参数的DIBIT提取

    公开(公告)号:US20120026623A1

    公开(公告)日:2012-02-02

    申请号:US12845110

    申请日:2010-07-28

    IPC分类号: G11B5/09

    摘要: In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response.

    摘要翻译: 在一个实施例中,一种用于估计存储设备的一个或多个信道参数的存储设备实现的方法,所述存储设备包括读取通道和具有存储在存储介质上的位序列的存储介质。 该方法包括:(a)存储装置从存储介质中读取比特序列的至少一部分以产生比特响应; (b)所述存储装置卷积所述位响应以计算所述读通道的脉冲响应; 以及(c)所述存储装置基于所计算的脉冲响应来估计一个或多个信道参数。

    Fly-height control using asynchronous sampling
    9.
    发明授权
    Fly-height control using asynchronous sampling 有权
    飞高控制采用异步采样

    公开(公告)号:US08077427B2

    公开(公告)日:2011-12-13

    申请号:US12758122

    申请日:2010-04-12

    IPC分类号: G11B5/60

    摘要: In one embodiment, a hard-disk drive system performs fly-height control using a read-back mode and a loop-back mode. The read-back mode measures first and second harmonics pre-recorded on the medium and divides the first measurement by the second to obtain a read-back mode harmonic ratio. The loop-back mode measures the same first and second harmonics; however, the harmonics are provided by a write precompensation circuit rather than the medium. Further, the loop-back mode measurements are performed using asynchronous sampling to address aliasing and quantization errors. The first measurement is divided by the second to generate a loop-back harmonic ratio. In logarithm domain, the loop-back ratio is subtracted from the read-back mode ratio to remove environment-induced variations in the read path electronic circuits. The resulting harmonic ratio is subtracted from an initial harmonic ratio determined, for example, during manufacturing, to determine how much the harmonic ratio has changed.

    摘要翻译: 在一个实施例中,硬盘驱动器系统使用回读模式和循环模式来执行飞行高度控制。 回读模式测量在介质上预先记录的第一和第二次谐波,并将第一次测量除以秒,以获得回读模式谐波比。 环回模式测量相同的第一和第二谐波; 然而,谐波由写入预补偿电路而不是介质提供。 此外,使用异步采样来执行环回模式测量以解决混叠和量化误差。 第一次测量除以二次以产生回路谐波比。 在对数域中,从回读模式比率中减去回路比,以消除读取路径电子电路中的环境引起的变化。 从制造时例如确定的初始谐波比减去得到的谐波比,以确定谐波比已经改变了多少。

    Systems and Methods for Determining Noise Components in a Signal Set
    10.
    发明申请
    Systems and Methods for Determining Noise Components in a Signal Set 有权
    用于确定信号组噪声分量的系统和方法

    公开(公告)号:US20110164669A1

    公开(公告)日:2011-07-07

    申请号:US12652201

    申请日:2010-01-05

    IPC分类号: H04B17/00

    CPC分类号: G11B20/10046 H04B17/345

    摘要: Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples.

    摘要翻译: 本发明的各种实施例提供了用于估计接收信号组中的噪声分量的系统和方法。 例如,本发明的一个实施例提供了一种包括数据检测器电路和噪声分量计算电路的噪声估计电路。 数据检测器电路接收一系列数据样本并提供检测的输出,并且噪声分量计算电路提供电子噪声功率输出和媒体噪声功率输出,每个至少部分地基于所检测的输出和数据系列计算 样品。