Systems and methods for equalizer optimization in a storage access retry
    1.
    发明授权
    Systems and methods for equalizer optimization in a storage access retry 有权
    存储访问重试中均衡器优化的系统和方法

    公开(公告)号:US07948699B2

    公开(公告)日:2011-05-24

    申请号:US12348236

    申请日:2009-01-02

    IPC分类号: G11B5/09

    摘要: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.

    摘要翻译: 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。

    Systems and Methods for Equalizer Optimization in a Storage Access Retry
    2.
    发明申请
    Systems and Methods for Equalizer Optimization in a Storage Access Retry 有权
    存储访问重试中均衡器优化的系统和方法

    公开(公告)号:US20100172046A1

    公开(公告)日:2010-07-08

    申请号:US12348236

    申请日:2009-01-02

    IPC分类号: G11B20/10

    摘要: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.

    摘要翻译: 本发明的各种实施例提供了包括多路复用器,存储器缓冲器,数据处理电路和通道设置修改电路的数据处理电路。 多路复用器的第一输入接收输入数据集,多路复用器的第二输入接收缓冲数据集。 复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。 存储器缓冲器接收多路复用器输出并提供缓冲数据集。 数据处理电路的操作至少部分由通道设置决定。 数据处理电路接收复用器输出并执行数据检测处理。 当数据检测过程失败时,选择信号被置位以选择缓冲数据集,当数据检测过程成功时,选择信号选择输入数据集。 当数据检测处理失败时,通道设置修改电路可操作以修改通道设置。

    Methods and apparatus for selective data retention decoding in a hard disk drive
    4.
    发明授权
    Methods and apparatus for selective data retention decoding in a hard disk drive 有权
    用于在硬盘驱动器中进行选择性数据保存解码的方法和装置

    公开(公告)号:US08225183B2

    公开(公告)日:2012-07-17

    申请号:US12241919

    申请日:2008-09-30

    IPC分类号: H03M13/00

    摘要: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

    摘要翻译: 提供了用于改进硬盘驱动器中物理重读操作的方法和装置。 所公开的方法和设备选择性地将数据保留在硬盘驱动器中。 通过将读取信号中的多个段中的每一个分配可靠度度量,在迭代读取通道中读取信号; 重复多个读取操作的分配步骤; 并且基于所分配的可靠性度量选择性地保留段。 可以通过将传感器定位在存储介质上来获得读取信号。 可靠性度量可以基于软比特决策; 对数似然比或给定段的噪声估计。

    Methods and Apparatus for Selective Data Retention Decoding in a Hard Disk Drive
    5.
    发明申请
    Methods and Apparatus for Selective Data Retention Decoding in a Hard Disk Drive 有权
    用于硬盘驱动器中选择性数据保留解码的方法和装置

    公开(公告)号:US20100083075A1

    公开(公告)日:2010-04-01

    申请号:US12241919

    申请日:2008-09-30

    IPC分类号: H03M13/05 G06F11/14

    摘要: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

    摘要翻译: 提供了用于改进硬盘驱动器中物理重读操作的方法和装置。 所公开的方法和设备选择性地将数据保留在硬盘驱动器中。 通过将读取信号中的多个段中的每一个分配可靠度度量,在迭代读取通道中读取信号; 重复多个读取操作的分配步骤; 并且基于所分配的可靠性度量选择性地保留段。 可以通过将传感器定位在存储介质上来获得读取信号。 可靠性度量可以基于软比特决策; 对数似然比或给定段的噪声估计。

    AGC Loop with Weighted Zero Forcing and LMS Error Sources and Methods for Using Such
    6.
    发明申请
    AGC Loop with Weighted Zero Forcing and LMS Error Sources and Methods for Using Such 有权
    具有加权零强制和LMS误差源的AGC环路及其使用方法

    公开(公告)号:US20100177419A1

    公开(公告)日:2010-07-15

    申请号:US12352540

    申请日:2009-01-12

    IPC分类号: G11B5/00 H03G3/30

    摘要: Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

    摘要翻译: 本发明的各种实施例提供用于增益控制的系统和方法。 例如,本发明的一些实施例提供可变增益控制电路。 这种电路包括产生零强制反馈的零强制环路和产生最小均方反馈的最小均方环路。 误差量化电路使用零强制反馈和最小均方反馈基于阈值条件产生混合反馈。 可变增益放大器至少部分地由混合反馈的导数来控制。

    AGC loop with weighted zero forcing and LMS error sources and methods for using such
    7.
    发明授权
    AGC loop with weighted zero forcing and LMS error sources and methods for using such 有权
    具有加权零强制和LMS误差源的AGC环路及其使用方法

    公开(公告)号:US07872823B2

    公开(公告)日:2011-01-18

    申请号:US12352540

    申请日:2009-01-12

    IPC分类号: G11B5/09

    摘要: Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.

    摘要翻译: 本发明的各种实施例提供用于增益控制的系统和方法。 例如,本发明的一些实施例提供可变增益控制电路。 这种电路包括产生零强制反馈的零强制环路和产生最小均方反馈的最小均方环路。 误差量化电路使用零强制反馈和最小均方反馈基于阈值条件产生混合反馈。 可变增益放大器至少部分地由混合反馈的导数来控制。

    Dibit pulse extraction methods and systems
    8.
    发明授权
    Dibit pulse extraction methods and systems 有权
    Dibit脉冲提取方法和系统

    公开(公告)号:US08441751B1

    公开(公告)日:2013-05-14

    申请号:US11840682

    申请日:2007-08-17

    IPC分类号: G11B5/09

    摘要: A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.

    摘要翻译: 接收设备可以被配置为使用在接收设备的基本读取的信道符号率处采样的符号来导出过采样的双位脉冲响应估计。 接收设备可以包括数据获取电路,其被配置为数字化从存储介质导出的数据,符号定时循环和读取电路,以及配置为使用在读取通道上采样的符号来估计过采样双位脉冲响应的双位脉冲估计电路 接收设备的速率,而不会干扰符号定时循环和读取电路。

    Branch-metric calibration using varying bandwidth values
    9.
    发明授权
    Branch-metric calibration using varying bandwidth values 有权
    使用不同带宽值的分支校准校准

    公开(公告)号:US08312359B2

    公开(公告)日:2012-11-13

    申请号:US12562200

    申请日:2009-09-18

    IPC分类号: H03M13/03 G06F11/00

    摘要: In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

    摘要翻译: 在一个实施例中,信号处理接收机具有分支量测校准(BMC)单元,其接收(i)来自信道检测器的四个硬判决位的集合,以及(ii)噪声估计。 BMC单元具有两个或多个更新块(例如抽头重量更新和/或偏置补偿块),其生成由信道检测器的分支度量单元使用的更新参数以改善信道检测。 两个或多个更新块基于(i)四个硬判决位的集合,(ii)噪声估计和(iii)带宽值)来生成更新的参数。 选择两个或多个更新块中的至少两个的带宽值使得它们彼此不同。 选择不同的带宽值可以通过选择彼此相同的带宽值来实现的比特错误率降低接收机的比特误码率。

    Detector for low frequency offset distortion
    10.
    发明授权
    Detector for low frequency offset distortion 失效
    低频偏移失真检测器

    公开(公告)号:US08537883B1

    公开(公告)日:2013-09-17

    申请号:US13365712

    申请日:2012-02-03

    IPC分类号: H03H7/30

    摘要: A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

    摘要翻译: 一种用于从数字信号中去除低频偏移失真的系统,该系统包括用于将与光学存储介质相关联的模拟频率信号转换为数字频率信号的模拟 - 数字转换器; 均衡器以均衡数字频率信号; 用于估计数字频率信号的低频偏移失真的估计器; 补偿器,用于使用所述估计从所述均衡数字频率信号基本上消除所述数字频率信号的低频偏移失真; 以及解码器,用于解码具有基本上从其中抵消的低频偏移失真的均衡数字频率信号。