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1.发明授权Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache 失效缓存存储系统采用虚拟地址主指令和数据高速缓存以及物理地址二级缓存
公开(公告)号：US5542062A
公开(公告)日：1996-07-30
申请号：US172684
申请日：1993-12-22
CPC分类号： G06F12/0891 , G06F12/0888 , G06F12/0897 , G06F12/1045
摘要： A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
摘要翻译： 一种用于计算机系统的两级缓存存储器系统，包括两个主缓存存储器，一个用于存储指令，一个用于存储数据。 该系统还包括用于存储指令和数据的二级高速缓冲存储器。 主缓存和辅助缓存每个使用自己的单独的标签目录。 主缓存使用采用虚拟标签和虚拟地址的虚拟寻址方案。 二级缓存采用使用虚拟标签和部分物理地址的混合寻址方案。 主缓存和副缓存并行运行，除非较大和较慢的二级缓存正在执行先前的操作。 只有在主缓存和副缓存中遇到“未命中”，系统处理器才能访问主内存。
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公开(公告)号：US5307477A
公开(公告)日：1994-04-26
申请号：US59715
申请日：1993-05-10
CPC分类号： G06F12/0891 , G06F12/0888 , G06F12/0897 , G06F12/1045
摘要： A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
摘要翻译： 一种用于包括两个主高速缓冲存储器的计算机系统的两级缓存存储器系统，一个用于存储指令，一个用于存储数据。 该系统还包括用于存储指令和数据的二级高速缓冲存储器。 主缓存和辅助缓存每个使用自己的单独的标签目录。 主缓存使用采用虚拟标签和虚拟地址的虚拟寻址方案。 二级缓存采用使用虚拟标签和部分物理地址的混合寻址方案。 主缓存和副缓存并行运行，除非较大和较慢的二级缓存正在执行先前的操作。 只有在主缓存和副缓存中遇到“未命中”，系统处理器才能访问主内存。
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公开(公告)号：US5699551A
公开(公告)日：1997-12-16
申请号：US484313
申请日：1995-06-07
CPC分类号： G06F12/0891 , G06F12/0888 , G06F12/0897 , G06F12/1045
摘要： A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.
摘要翻译： 一种使多级高速缓冲存储器系统的每个级别中的指定高速缓存中的行无效的方法。 高速缓冲存储器系统的每一行包括标签字段，数据字段和指示该行的有效性的位。 该方法提供了绕过任何地址转换机制的软件无效指令。 软件无效指令中包含的第一个字段用于标识要避免多行缓存的行。 生成目标地址以对高速缓冲存储器系统的每个级别进行索引。 该位的状态根据地址和无效指令而改变。
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公开(公告)号：US5056110A
公开(公告)日：1991-10-08
申请号：US448715
申请日：1989-12-11
申请人： Timonty S. Fu , Allen W. Roberts
发明人： Timonty S. Fu , Allen W. Roberts
CPC分类号： H04L12/40006 , H04L25/0298
摘要： A solution to the problem in differential buses that the bus state for a given line pair is undefined when no unit is driving either of the bus lines in the pair. The lines in the bus pair are terminated to different voltage levels, thereby establishing a desired default condition when no unit is driving either line. The voltage offset between the two bus lines must be sufficient that differential receivers coupled to the bus when the bus is not driven can respond to the offset. At the same time, the offset must not be so great that a driver attempting to drive the bus pair cannot overcome the offset with enough margin for the receivers.
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公开(公告)号：US4481625A
公开(公告)日：1984-11-06
申请号：US313524
申请日：1981-10-21
CPC分类号： H03K5/02 , G06F13/40 , G06F13/42 , H03F3/45071
摘要： In a high speed data bus system, each functional unit has an associated port which operates to accept all related information that makes up a communication, or if this cannot be done, to accept none of the information. More particularly, an information transfer, depending on its nature, may comprise one BIQ or more than one BIQ (a "BIQ" is a bus information quantum which is placed on the bus for one bus cycle). To implement the indivisibility of multiple-BIQ transfers, the control logic for each port includes screening circuitry responsive to the state of the port's input buffers, and further responsive to flags from the functional unit for selectively accepting or rejecting BIQ's, and further includes screening constraint circuitry to ensure that the port accepts all or none of the BIQ's that make up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers (for example, operations).
摘要翻译： 在高速数据总线系统中，每个功能单元具有相关联的端口，其操作以接受构成通信的所有相关信息，或者如果不能完成，则不接受任何信息。 更具体地，取决于其性质的信息传输可以包括一个BIQ或多于一个BIQ（“BIQ”是总线信息量子，其布置在总线上一个总线周期）。 为了实现多个BIQ传输的不可分割性，每个端口的控制逻辑包括响应于端口输入缓冲器的状态的屏蔽电路，并且进一步响应来自功能单元的标志以选择性地接受或拒绝BIQ，并且还包括屏蔽约束 确保端口接受组成传输的全部或者任何BIQ的电路。 根据标志，拒绝可能是全部的，或者可能仅适用于指定类别的转移（例如，操作）。
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