公开(公告)号：US5031180A

公开(公告)日：1991-07-09

申请号：US336499

申请日：1989-04-11

Applicant: George W. McIver ,  John R. Marum ,  James B. Cho

Inventor： George W. McIver ,  John R. Marum ,  James B. Cho

IPC: G06F11/18

CPC classification number: G06F11/183

Abstract: A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.

Abstract translation: 一个容错寄存器，采用三重数据冗余存储和连续投票，以保护单事件不正常或SEU的数据。 容错寄存器包括单个主复用器，与主复用器的输出并联连接的三个从属多路复用器和位于从属多路复用器的反馈路径中的三个投票电路。 从属多路复用器为数据提供三重冗余存储，并且投票电路可以纠正任何可能中断的数据。 本发明的容错寄存器提供大大提高的SEU容限，而不会大大增加电路面积，或者不采用纠错及其伴随的擦洗过程。

公开(公告)号：US4849847A

公开(公告)日：1989-07-18

申请号：US135476

申请日：1987-12-21

Applicant: George W. McIver ,  James B. Cho

Inventor： George W. McIver ,  James B. Cho

IPC: H02H3/087 ,  G06F11/00

CPC classification number: G11C29/025 ,  G06F11/0754 ,  G11C29/006 ,  G11C29/12 ,  G11C29/12005 ,  G11C5/14 ,  G11C2029/5006

Abstract: An adjunct switch circuit is provided for detecting power to ground leaks in a portion of a chip circuit and for disabling such circuit portion in the event of a leak. The switch circuit of the invention is particularly useful for Wafer Scale Integration, and is conveniently employed in the testing of chip circuits following manufacturing.In a preferred embodiment, the switch circuit includes a power supply, including a voltage source and a ground, a reset line for receiving a reset pulse, a first switch, connected in series with one of the power supply lines to the circuit portion ground and inversely responsive to both the reset pulse and the state of the circuit portion ground following termination of the reset pulse, and a second switch, connected between ground and the circuit portion ground and directly responsive to the reset pulse to leak current from the circuit portion ground to ground when turned on by the reset pulse.

Abstract translation: 提供了一个辅助开关电路，用于检测芯片电路的一部分中的接地泄漏电力，并在发生泄漏的情况下禁止这种电路部分。 本发明的开关电路对于晶片尺寸积分特别有用，并且在制造后的芯片电路的测试中方便地使用。 在优选实施例中，开关电路包括电源，包括电压源和接地，用于接收复位脉冲的复位线，与电源部分接地中的一条电源线串联连接的第一开关，以及 在复位脉冲终止之后对复位脉冲和电路部分接地的状态两者产生反向响应，以及第二开关，其连接在接地和电路部分接地之间，并且直接响应于复位脉冲而从电路部分地面泄漏电流 在复位脉冲打开时接地。

公开(公告)号：US07050463B1

公开(公告)日：2006-05-23

申请号：US09703430

申请日：2000-10-31

Applicant: James B. Cho ,  Harry W. Hartjes

Inventor： James B. Cho ,  Harry W. Hartjes

IPC: H04J3/00

CPC classification number: H04J3/0608 ,  H04J2203/0089 ,  H04L25/0262 ,  Y10S370/907

Abstract: An automatic bit-rate detection scheme (30) for use in SONET/SDH transceivers (12, 14) that uses only one clocking frequency (clk), is all digital, and requires less than 250 microseconds to detect a new data bit-rate. The present invention analyzes events that are guaranteed to be present in all SONET data streams. A1 and A2 framing bytes (22,24) occur at 125 microseconds intervals in all SONET signals. The bit transitions in the framing bytes represent the minimum transition intervals of the received data. The present invention examines this bit interval to determine the operating frequency of the received data. A set of combinational logic circuits (70, 80, 90) are used to detect specific data bit patterns which appear in the A1 and A2 SONET framing bytes, such as “010” and “101”. The combinational circuit looks for specific patterns of data bits occurring at a specific communication rate. Latches (76, 86, 96) capture the pulses that are generated by the combinational circuits each time that the particular bit pattern is detected. After sufficient time is passed, the output of the capturing latches indicates which data rates have been detected and logic determines the received data bit-rate, (52, 100). A multi-rate chip is then responsively set to communicate at the highest rate detected. The data can be shifted in serially or in parallel.

Abstract translation: 用于仅使用一个时钟频率（clk）的SONET / SDH收发器（12,14）中的自动比特率检测方案（30）全部是数字的，并且需要小于250微秒来检测新的数据比特率 。 本发明分析保证存在于所有SONET数据流中的事件。 A1和A2成帧字节（22,24）在所有SONET信号中以125微秒的间隔发生。 成帧字节中的位转换表示接收数据的最小转换间隔。 本发明检查该位间隔以确定接收数据的工作频率。 一组组合逻辑电路（70,80,90）用于检测出现在A1和A2 SONET成帧字节（例如“010”和“101”）中的特定数据位模式。 组合电路寻找以特定通信速率发生的数据位的特定模式。 锁存器（76,86,96）每次检测到特定位模式时捕获组合电路产生的脉冲。 在经过足够的时间之后，捕获锁存器的输出指示哪个数据速率被检测到并且逻辑确定接收的数据比特率（52,100）。 然后响应地设置多速率芯片以以最高速率进行通信。 数据可以串行或并行移位。

公开(公告)号：US07443935B2

公开(公告)日：2008-10-28

申请号：US10286925

申请日：2002-11-02

Applicant: James B. Cho

Inventor： James B. Cho

IPC: H04L27/06 ,  H04L7/00

CPC classification number: H04L7/0083 ,  H04L7/0025

Abstract: An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the receiver clock parameter and generating a tracking parameter for comparing the receiver clock parameter and periodicity of the local clock; (d) a counter for counting events associated with the tracking parameter and generating an event count relating to the received signals; (e) a decision unit for reckoning the event count and generate a decision parameter relating to the reckoning; and (f) output logic coupled with the decision unit, the tracker and the receiver clock for evaluating the decision parameter and the tracking parameter by a logical routine for determining a need for changing operation of the receiver clock and for generating a change signal when the need exists.

Abstract translation: 一种用于调整接收机带宽的装置，包括：（a）接收机时钟，根据与接收信号相关的接收机时钟参数进行操作，用于对接收的信号进行采样; （b）当地时钟; （c）跟踪器，接收与所述接收机时钟参数相关的指示符，并产生用于比较所述接收机时钟参数和所述本地时钟的周期性的跟踪参数; （d）计数器，用于对与所述跟踪参数相关联的计数事件并产生与所述接收信号有关的事件计数; （e）用于计算事件计数并产生与推算相关的判定参数的判定单元; 和（f）与判定单元耦合的输出逻辑，跟踪器和接收器时钟，用于通过逻辑例程来评估判定参数和跟踪参数，用于确定需要改变接收机时钟的操作，并且用于当 需要存在。

公开(公告)号：US07323917B2

公开(公告)日：2008-01-29

申请号：US10662596

申请日：2003-09-15

Applicant: James B. Cho ,  Christian Harrieder

Inventor： James B. Cho ,  Christian Harrieder

IPC: H04L7/00

CPC classification number: H03K5/135 ,  H03K2005/00052

Abstract: An apparatus and method of synthesizing an output clock signal from a source clock signal. The clock synthesizer includes a phase generator, a phase selector, a phase interpolator, and control circuitry for controlling the phase selector/interpolator. The phase generator receives a high speed clock, and generates P phases of the source clock to define P phase sectors. The phase selector selects respective pairs of phases such that each pair bounds a respective phase sector. The phase interpolator introduces at least one phase of the source clock between each pair of phases to provide Q phases of the source clock within each sector. The phase interpolator uses the phases of the source clock to produce lagging (leading) phase shifts of 360/P(Q−1) degrees, thereby generating the output clock having a stepped up or stepped down frequency.

Abstract translation: 一种从源时钟信号合成输出时钟信号的装置和方法。 时钟合成器包括相位发生器，相位选择器，相位内插器和用于控制相位选择器/内插器的控制电路。 相位发生器接收高速时钟，并产生源时钟的P相以定义P相扇区。 相位选择器选择各对相位，使得每对限制相应的相位扇区。 相位插值器在每对相位之间引入源时钟的至少一个相位，以在每个扇区内提供源时钟的Q个相位。 相位内插器使用源时钟的相位产生360 / P（Q-1）度的滞后（前导）相移，从而产生具有升压或降压频率的输出时钟。

公开(公告)号：US06856661B2

公开(公告)日：2005-02-15

申请号：US09801534

申请日：2001-03-08

Applicant: James B. Cho

Inventor： James B. Cho

IPC: H03L7/081 ,  H03L7/095 ,  H04L7/00 ,  H04L7/033 ,  H04L25/00

CPC classification number: H03L7/095 ,  H03L7/081 ,  H04L7/0083 ,  H04L7/0337

Abstract: A loss of lock condition of a clock signal (25) recovered from a received data stream can be detected by examining conventionally available information (25, 26) indicative of a rate of change of an interpolation ratio according to which first and second phases of a local reference clock signal are combined to form the recovered clock signal.

Abstract translation: 可以通过检查表示内插比率的变化率的常规可用信息（25,26）来检测从接收到的数据流恢复的时钟信号（25）的锁定状态的损失，根据第一和第二阶段 本地参考时钟信号被组合以形成恢复的时钟信号。