利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.05 秒)

    Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file
    9.
    发明授权
    Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file 有权
    使用加载和存储地址生成器访问存储库中的表，共享存储与地址寄存器文件分离的计算寄存器文件的读取端口

    公开(公告)号：US06397324B1

    公开(公告)日：2002-05-28

    申请号：US09596103

    申请日：2000-06-16

    申请人： Edwin Frank Barry ,  Charles W. Kurak, Jr. ,  Gerald G. Pechanek ,  Larry D. Larsen

    发明人： Edwin Frank Barry ,  Charles W. Kurak, Jr. ,  Gerald G. Pechanek ,  Larry D. Larsen

    IPC分类号： G06F9312

    CPC分类号： G06F9/3004 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3885 ,  H03M7/425

    摘要： A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers. The present approach provides an efficient mechanism for supporting these functions while maintaining separate compute and address register files.

    摘要翻译： 由于并行执行包括VLIW的子指令，很长的指令字（VLIW）处理器通常需要大量的寄存器文件端口。 通过将通用寄存器文件分割成单独的地址和计算寄存器文件，计算寄存器文件端口的数量大大减少。 当支持具有索引寻址模式的多个加载和存储执行单元时，这种减少尤其明显。 这意味着在编程模型中实现了更快的寄存器文件和专用地址寄存器。 节省成本是为计算寄存器文件和地址寄存器文件之间的数据移动提供支持。 此外，地址算术，表查找和存储到表函数是当地址寄存器与计算寄存器分离时不能明显获得的所需函数。 本方法提供了一种支持这些功能的有效机制，同时保持单独的计算和地址寄存器文件。

    Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
    10.
    发明申请
    Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 有权
    用于可扩展阵列处理器中断检测和响应的方法和装置

    公开(公告)号：US20080222333A1

    公开(公告)日：2008-09-11

    申请号：US12120543

    申请日：2008-05-14

    申请人： Edwin Frank Barry ,  Patrick R. Marchand ,  Gerald G. Pechanek ,  Larry D. Larsen

    发明人： Edwin Frank Barry ,  Patrick R. Marchand ,  Gerald G. Pechanek ,  Larry D. Larsen

    IPC分类号： G06F13/24 ,  G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/3865 ,  G06F9/30058 ,  G06F9/3861 ,  G06F9/4812 ,  G06F11/27 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

    摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.

    摘要翻译： 描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。 利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。 当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。 支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。 此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。