公开(公告)号：US12008532B2

公开(公告)日：2024-06-11

申请号：US17178002

申请日：2021-02-17

Applicant: Geum-Cheol Kim

Inventor： Geum-Cheol Kim

IPC: G06Q20/20 ,  G06Q20/40

CPC classification number: G06Q20/202 ,  G06Q20/4014

Abstract: Not using any app, a URL medium including a vault URL containing a property of an ID of a user is used during a user confirmation process and a transaction request process (a payment request process or a charging request process), and transaction (a payment or a charging) is made using money from an external device (a URL vault account), not the URL medium. A URL medium can support a way of requesting a transaction (a payment or a charging) after checking a user, or can support a way of confirming a user after requesting a transaction (a payment or a charging). A URL medium can support offline transactions and online transactions, and two URL medium (a URL medium-B of a buyer and a URL medium-S of a seller) can support offline transactions that do not use a POS (a URL POS). A URL medium can also support transactions that temporarily approve a payment.

公开(公告)号：US5901335A

公开(公告)日：1999-05-04

申请号：US880109

申请日：1997-06-20

Applicant: Geum-Cheol Kim

Inventor： Geum-Cheol Kim

IPC: H04N5/04 ,  H03K19/00 ,  H03M9/00 ,  H04J3/06 ,  H04L7/04 ,  H04N7/56 ,  H04N19/00 ,  H04N19/70 ,  G06F3/00

CPC classification number: H04J3/0608

Abstract: A circuit for detecting a synchronous word signal from a moving picture experts group (MPEG) bit stream in a video-audio decoding system which is capable of more easily detecting a synchronous word by detecting a data start position of an input bit stream used for a multimedia system using the moving picture experts group (MPEG) detecting identical level bits from a bit stream inputted, and comparing the bits at a time. The circuit includes a serial/parallel converter for converting a data of a synchronous signal transmitted thereto in series in a bit stream form into a parallel data in accordance with a clock signal inputted thereinto, a separating and comparing unit for separating identical level bit signals of a synchronous word from an output signal from the serial/parallel converter and generating a flag signal when the signal is detected, a controller for judging an input of a synchronous word as a flag signal and generating a data processing control signal, and a data processor for processing a parallel output signal from the serial/parallel converter in accordance with a data processing control signal from the controller and outputting a data.

Abstract translation: 一种用于从视频 - 音频解码系统中的运动图像专家组（MPEG）比特流中检测同步字信号的电路，该电视音频解码系统能够通过检测用于一个输入比特流的输入比特流的数据开始位置来更容易地检测同步字 多媒体系统使用运动图像专家组（MPEG）从输入的比特流检测相同的等级比特，并且一次比较比特。 该电路包括串行/并行转换器，用于根据输入的时钟信号，以位流形式将发送到其的同步信号的数据串行转换为并行数据;分离和比较单元，用于分离 来自串行/并行转换器的输出信号的同步字，当检测到信号时产生标志信号;控制器，用于判断同步字的输入作为标志信号，并产生数据处理控制信号;数据处理器 用于根据来自控制器的数据处理控制信号处理来自串行/并行转换器的并行输出信号并输出​​数据。