公开(公告)号：US10043889B2

公开(公告)日：2018-08-07

申请号：US15723729

申请日：2017-10-03

申请人： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

发明人： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L29/40 ,  H01L21/3105

CPC分类号： H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

摘要： The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

公开(公告)号：US20160240630A1

公开(公告)日：2016-08-18

申请号：US14988867

申请日：2016-01-06

申请人： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

发明人： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

IPC分类号： H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L29/40 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

摘要： The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

摘要翻译： 本发明构思涉及一种半导体器件及其制造方法。 半导体器件包括从衬底突出的有源图案，设置在衬底上的层间介电层，并且包括暴露有源图案的沟槽和沟槽中的栅电极。 凹槽包括具有第一宽度的第一凹槽和具有大于第一宽度的第二宽度的第二凹槽。 栅电极包括第一沟槽中的第一栅极电极和第二沟槽中的第二栅电极。 第一和第二栅电极中的每一个包括底表面上的第一功函导电图案和第一沟槽和第二沟槽中相应一个的侧壁，以及第一功函导电图案上的第二功函导电图案。