公开(公告)号：US10043889B2

公开(公告)日：2018-08-07

申请号：US15723729

申请日：2017-10-03

Applicant: GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

Inventor： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L29/40 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

公开(公告)号：US20150325575A1

公开(公告)日：2015-11-12

申请号：US14639494

申请日：2015-03-05

Applicant: Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Abstract translation: 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US20210213196A1

公开(公告)日：2021-07-15

申请号：US17166372

申请日：2021-02-03

Applicant: Luis Malave ,  Jesse Jaejin Kim ,  Yong Ho Jeon ,  Dong Min Lee

Inventor： Luis Malave ,  Jesse Jaejin Kim ,  Yong Ho Jeon ,  Dong Min Lee

IPC: A61M5/168 ,  A61M5/172 ,  G16H20/17

Abstract: Provided are a method, apparatus, and computer program for providing a notification according to a period of use of a drug infusion device. A time point at which the drug infusion device switches from an inactive mode to an active mode may be determined as a use start time point. Also, an impending expiration notification indicating that expiration of a period of use of the drug infusion device is imminent may be provided at a first time point after a certain period from the use start time point, based on a usable period and a user set time of the drug infusion device. In addition, an expiration notification indicating that the period of use of the drug infusion device has expired may be provided at a second time point after the usable period from the use start time point.

公开(公告)号：US08822341B2

公开(公告)日：2014-09-02

申请号：US13164090

申请日：2011-06-20

Applicant: Yong-Ho Jeon ,  Dong-Hyun Kim ,  Je-Woo Han ,  Kyoung-Sub Shin

Inventor： Yong-Ho Jeon ,  Dong-Hyun Kim ,  Je-Woo Han ,  Kyoung-Sub Shin

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/30655 ,  H01L21/76898

Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.

Abstract translation: 用于等离子体蚀刻的第一气体和用于等离子体沉积的第二气体被引入到半导体衬底上，该半导体衬底包括掩模图案。 第一气体和第二气体的流量在处理循环期间的流量范围内周期性地变化，使得等离子体蚀刻工艺和等离子体沉积工艺一起进行以在半导体衬底中形成开口。

公开(公告)号：US20110318930A1

公开(公告)日：2011-12-29

申请号：US13164090

申请日：2011-06-20

Applicant: Yong-Ho Jeon ,  Dong-Hyun Kim ,  Je-Woo Han ,  Kyoung-Sub Shin

Inventor： Yong-Ho Jeon ,  Dong-Hyun Kim ,  Je-Woo Han ,  Kyoung-Sub Shin

IPC: H01L21/306 ,  C23F1/00

CPC classification number: H01L21/30655 ,  H01L21/76898

Abstract: A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate.

Abstract translation: 用于等离子体蚀刻的第一气体和用于等离子体沉积的第二气体被引入到半导体衬底上，该半导体衬底包括掩模图案。 第一气体和第二气体的流量在处理循环期间的流量范围内周期性地变化，使得等离子体蚀刻工艺和等离子体沉积工艺一起进行以在半导体衬底中形成开口。

公开(公告)号：US12115349B2

公开(公告)日：2024-10-15

申请号：US17166372

申请日：2021-02-03

Applicant: Luis Malave ,  Jesse Jaejin Kim ,  Yong Ho Jeon ,  Dong Min Lee

Inventor： Luis Malave ,  Jesse Jaejin Kim ,  Yong Ho Jeon ,  Dong Min Lee

IPC: A61M5/168 ,  A61M5/172 ,  G16H20/17

CPC classification number: A61M5/1684 ,  A61M5/1723 ,  G16H20/17

Abstract: Provided are a method, apparatus, and computer program for providing a notification according to a period of use of a drug infusion device. A time point at which the drug infusion device switches from an inactive mode to an active mode may be determined as a use start time point. Also, an impending expiration notification indicating that expiration of a period of use of the drug infusion device is imminent may be provided at a first time point after a certain period from the use start time point, based on a usable period and a user set time of the drug infusion device. In addition, an expiration notification indicating that the period of use of the drug infusion device has expired may be provided at a second time point after the usable period from the use start time point.

公开(公告)号：US09299700B2

公开(公告)日：2016-03-29

申请号：US14639494

申请日：2015-03-05

Applicant: Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Abstract translation: 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US20140054713A1

公开(公告)日：2014-02-27

申请号：US13751570

申请日：2013-01-28

Applicant: Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

Inventor： Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/1211

Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。

公开(公告)号：US20110284163A1

公开(公告)日：2011-11-24

申请号：US13086475

申请日：2011-04-14

Applicant: Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

Inventor： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

IPC: H01L21/00 ,  C23F1/08

CPC classification number: H01L21/67069 ,  H01J37/32935 ,  H01J37/32972

Abstract: A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.

Abstract translation: 等离子体处理装置包括用于处理基板的室。 提供等离子体发生器以在腔室内产生等离子体。 窗口设置在室的侧壁中，并且窗口从腔室内的等离子体透射光。 在窗的内表面上提供光催化层，使得光催化层由于暴露于等离子体的光而被激活，从而在窗的内表面上分解残留产物。

公开(公告)号：US20180033867A1

公开(公告)日：2018-02-01

申请号：US15723729

申请日：2017-10-03

Applicant: GeumJung SEONG ,  JinWook LEE ,  Dohyoung KIM ,  Sungwoo MYUNG ,  Jisoo OH ,  Yong-Ho JEON

Inventor： GeumJung SEONG ,  JinWook LEE ,  Dohyoung KIM ,  Sungwoo MYUNG ,  Jisoo OH ,  Yong-Ho JEON

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/49 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.