公开(公告)号：US06172931B2

公开(公告)日：2001-01-09

申请号：US09436089

申请日：1999-11-08

申请人： Gi-Won Cha ,  Kyu-Nam Lim

发明人： Gi-Won Cha ,  Kyu-Nam Lim

IPC分类号： G11C700

CPC分类号： G11C8/12 ,  G11C5/145

摘要： A semiconductor memory device with multi-bank structure, includes multiple voltage boosting circuits or internal power supply voltage generating circuits, each of which generates a high voltage to be provided to a bank. The respective voltage boosting circuits or internal power supply voltage generating circuits are sequentially selected under the control of a select signal generating circuit which generates select signals corresponding to the voltage boosting circuits by use of a row address strobe signal. According to the above-mentioned configuration, the number of the voltage boosting circuits is less than the number of banks in the memory device. Therefore, the area that the voltage boosting circuits or internal power supply voltage generating circuits occupy on a chip does not increase in proportion to the increase in the number of banks.

摘要翻译： 具有多组结构的半导体存储器件包括多个升压电路或内部电源电压产生电路，每个电压产生电路产生要提供给存储体的高电压。 各个升压电路或内部电源电压产生电路在选择信号发生电路的控制下依次选择，该选择信号产生电路通过使用行地址选通信号产生与升压电路相对应的选择信号。 根据上述配置，升压电路的数量小于存储器件中的存储体的数量。 因此，升压电路或内部电源电压产生电路在芯片上占据的面积与银行数量的增加成比例地增加。

公开(公告)号：US20050073341A1

公开(公告)日：2005-04-07

申请号：US10404136

申请日：2003-04-02

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： G11C5/14 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power up signal generator includes a signal converter for converting an applied external source voltage to a voltage applied at a trigger node when the external source voltage rises to a first threshold, and a current source for flowing a reference current from the trigger node. A first inverter connected to the trigger node outputs a low level signal when the trigger node voltage reaches a second threshold. A second inverter outputs a power up signal after receiving the low level signal from the first inverter. The signal converter may include a PMOS transistor configuration, such that the trip voltage of the power up signal generator is dependent only on a single MOSFET transistor threshold voltage.

摘要翻译： 上电信号发生器包括信号转换器，用于当外部源电压上升到第一阈值时将施加的外部源电压转换为施加在触发节点处的电压，以及用于使来自触发节点的参考电流流动的电流源。 连接到触发器节点的第一反相器在触发节点电压达到第二阈值时输出低电平信号。 第二反相器在从第一反相器接收到低电平信号之后输出上电信号。 信号转换器可以包括PMOS晶体管配置，使得上电信号发生器的跳闸电压仅取决于单个MOSFET晶体管阈值电压。

公开(公告)号：US06859405B2

公开(公告)日：2005-02-22

申请号：US10465634

申请日：2003-06-20

申请人： Bum-Jae Lee ,  Su-A Kim ,  Kyu-Nam Lim

发明人： Bum-Jae Lee ,  Su-A Kim ,  Kyu-Nam Lim

IPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C2207/065

摘要： A semiconductor memory device having a bit line sense amplifier connected to a bit line pair may include a precharge part to precharge first and second drive nodes of the bit line sense amplifier to an equal voltage level. The device may include a switching part operatively connecting the first and second precharge nodes to the first and second drive nodes in response to sense amplifier drive signals applied during a data non-access mode. To drive power in the bit line sense amplifier, the precharge voltage may be applied in a precharge state to precharge the first and second drive nodes to the equal voltage level, the device may shift from the precharge state to an operational state to cut off the applied precharge voltage, and driving voltages may be applied to the first and second drive nodes to power the bit line sense amplifier of the device.

摘要翻译： 具有连接到位线对的位线读出放大器的半导体存储器件可以包括预充电部分，以将位线读出放大器的第一和第二驱动节点预充电到相等的电压电平。 该装置可以包括切换部分，其响应于在数据非访问模式期间施加的读出放大器驱动信号，将第一和第二预充电节点可操作地连接到第一和第二驱动节点。 为了驱动位线读出放大器的电力，可以在预充电状态下施加预充电电压，以将第一和第二驱动节点预充电到等电压电平，器件可以从预充电状态转移到操作状态以切断 施加的预充电电压，并且可以向第一和第二驱动节点施加驱动电压以为器件的位线读出放大器供电。

公开(公告)号：US06845049B2

公开(公告)日：2005-01-18

申请号：US10313817

申请日：2002-12-05

申请人： Kyu-Nam Lim ,  Jei-Hwan Yoo ,  Young-Gu Kang ,  Jong-Won Lee ,  Jae-Yoon Shim

发明人： Kyu-Nam Lim ,  Jei-Hwan Yoo ,  Young-Gu Kang ,  Jong-Won Lee ,  Jae-Yoon Shim

IPC分类号： G11C11/409 ,  G11C7/04 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C7/06 ,  G11C7/22 ,  G11C7/227 ,  G11C2207/2281

摘要： A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices. Furthermore, the generating circuit generates a bit line sense enable signal with constant delay time that is immune from process changes, voltage fluctuations, and temperature fluctuations.

摘要翻译： 公开了一种具有位线检测使能信号发生电路的半导体存储器件。 半导体存储器件包括用于产生用于选择字线的字线选择信号的字线选择信号发生电路; 延迟电路，用于通过将信号延迟到所述字线选择信号发生电路产生字线选择信号所需的相同的时间周期来产生延迟信号; 以及施密特触发器，用于通过接收来自延迟电路的输出信号并连接到与用于使能字线的电压电平相同的电压电平的电源电压来产生字线使能检测信号。 本发明中的位线检测使能信号发生电路的布局面积比传统的半导体存储器件要小。 此外，发生电路产生具有恒定延迟时间的位线检测使能信号，其免受过程变化，电压波动和温度波动的影响。

公开(公告)号：US20050013176A1

公开(公告)日：2005-01-20

申请号：US10818692

申请日：2004-04-06

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C29/12 ,  H01L21/822 ,  G11C7/00

CPC分类号： G11C29/12005 ,  G11C5/145 ,  G11C11/4074 ,  G11C29/12

摘要： Provided is a circuit and method of generating a boosted voltage while maintaining a constant difference between the boosted voltage and an array reference voltage when the array reference voltage is varied in a normal mode, a test mode, and a burn-in test mode of a semiconductor device. The boosted voltage generating circuit comprises a sensing signal generating circuit which generates a sensing signal, a pulse generating circuit which generates a driving signal in response to the sensing signal, and a pumping circuit which generates the boosted voltage in response to the driving signal to control a word line of a semiconductor device. The sensing signal generating circuit comprises a comparator which includes a first input terminal, a second input terminal for receiving a reference voltage, and an output terminal for outputting the sensing signal, a resistor coupled between the boosted voltage and the first input terminal, and a constant current source coupled between the first input terminal and a ground voltage.

摘要翻译： 提供一种电路和方法，当阵列参考电压在正常模式，测试模式和老化测试模式下变化时，产生升压电压同时保持升压电压和阵列参考电压之间的恒定差异 半导体器件。 升压电压产生电路包括产生感测信号的感测信号发生电路，响应于感测信号产生驱动信号的脉冲发生电路，以及响应于驱动信号产生升压电压的泵浦电路以进行控制 半导体器件的字线。 感测信号发生电路包括比较器，该比较器包括第一输入端，用于接收参考电压的第二输入端和用于输出感测信号的输出端，耦合在升压电压和第一输入端之间的电阻，以及 耦合在第一输入端和接地电压之间的恒流源。

公开(公告)号：US06778007B2

公开(公告)日：2004-08-17

申请号：US10155196

申请日：2002-05-24

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： G05F110

CPC分类号： G05F1/465

摘要： An internal power voltage generating circuit capable of accurately adjusting a level of an internal power voltage in response to an overshoot of the internal power voltage. In one embodiment, the circuit comprises an internal power voltage generator for generating an internal power voltage to an internal power voltage generating terminal, first and second resistor devices, serially connected between the internal power voltage generating terminal and a ground voltage, for distributing the internal power voltage and for generating a distributed voltage to a distributed voltage generating node, and a current discharging device, connected between the internal power voltage generating terminal and the ground voltage, for discharging current from the internal power voltage generating terminal to the ground voltage in response to the distributed voltage.

摘要翻译： 一种内部电源电压发生电路，能够根据内部电源电压的过冲来精确地调整内部电力电压的电平。 在一个实施例中，该电路包括用于产生内部电源电压产生端的内部电源电压的内部电力电压发生器，串联连接在内部电源电压产生端子和接地电压之间的第一和第二电阻器件，用于分配内部电源电压 并且用于产生分布电压到分布式电压产生节点;以及电流放电装置，连接在内部电力电压产生端子和接地电压之间，用于响应于从内部电力电压产生端子将电流放电到接地电压 到分布电压。

公开(公告)号：US06535440B2

公开(公告)日：2003-03-18

申请号：US09906896

申请日：2001-07-16

申请人： Kyu-Nam Lim ,  Jong-hyun Choi ,  Sang-suk Kang

发明人： Kyu-Nam Lim ,  Jong-hyun Choi ,  Sang-suk Kang

IPC分类号： G11C700

CPC分类号： G11C29/56 ,  G01R31/319

摘要： An apparatus and a method are disclosed for package level burn-in test circuit in semiconductor devices. The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.

公开(公告)号：US06452429B1

公开(公告)日：2002-09-17

申请号：US09574306

申请日：2000-05-19

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： H03B100

CPC分类号： H04L25/0292 ,  H03K19/01707 ,  H03K19/018528

摘要： An input buffer circuit simultaneously supports a low voltage interface and a general low voltage transistor-transistor logic (LVTTL) interface and operates at high speed. In the input buffer circuit, a self bias voltage generated by a self biased differential amplification circuit is used not only for tracking a common mode input voltage in the differential amplification circuit but also for controlling the current of a current source and/or sink that controls the current used in the differential amplification circuit. Accordingly, the self bias voltage remains at a substantially uniform level. Therefore, the entire transconductance gain gm of the differential amplification circuit is substantially uniform regardless of the change in a reference voltage input to the differential amplification circuit. As a result, a low voltage interface characteristic is improved. The input buffer circuit can further include a swing width control circuit that responds to an inverted signal generated from the output signal of the differential amplification circuit and prevents the voltage swing of the output signal from becoming excessively large. This reduces skew and thus improves the operating speed of the input buffer.

摘要翻译： 输入缓冲电路同时支持低电压接口和一般的低电压晶体管晶体管逻辑（LVTTL）接口，并以高速运行。 在输入缓冲器电路中，由自偏压差分放大电路产生的自偏压不仅用于跟踪差分放大电路中的共模输入电压，而且用于控制控制电流源和/或电流的电流 差分放大电路中使用的电流。 因此，自偏压保持在基本均匀的水平。 因此，无论输入到差分放大电路的参考电压的变化如何，差分放大电路的整个跨导增益gm基本上是均匀的。 结果，提高了低电压接口特性。 输入缓冲电路还可以包括摆幅宽度控制电路，其响应于从差分放大电路的输出信号产生的反相信号，并防止输出信号的电压摆幅变得过大。 这减少了偏差，从而提高了输入缓冲器的工作速度。

公开(公告)号：US06721218B2

公开(公告)日：2004-04-13

申请号：US10075472

申请日：2002-02-13

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： G11C702

CPC分类号： G11C16/26

摘要： A device according to the invention includes memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.

摘要翻译： 根据本发明的装置包括存储单元和电流检测放大器。 它还包括一个反馈电路来调节电流检测放大器的增益。 根据存储在当前读出放大器上要读取的不同存储单元的数据的相对延迟来调节增益。

公开(公告)号：US06690613B2

公开(公告)日：2004-02-10

申请号：US10076235

申请日：2002-02-13

申请人： Kyu-Nam Lim

发明人： Kyu-Nam Lim

IPC分类号： G11C1630

CPC分类号： G11C5/145

摘要： A high voltage generating circuit includes a standby high voltage generating means and an active high voltage generating means. The standby high voltage generating means detects a level of a high voltage in both a standby mode and an active mode to boost the high voltage when the level of the high voltage is lower than a predetermined level. The active high voltage generating means varies a voltage boosting ability responsive to a control signal when an active command is applied in the active mode to thereby boost the level of the high voltage. The active high voltage generating means also detects whether the level of the high voltage is lower than the predetermined level to adjust a level of the control signal.

摘要翻译： 高压发生电路包括备用高压发生装置和有源高电压发生装置。 备用高压发生装置在高电压电平低于预定电平时，在待机模式和有功模式下都检测高电平，以升高高电压。 当在有源模式下施加有效指令时，有源高电压发生装置响应于控制信号改变升压能力，从而提高高电压电平。 有源高电压发生装置还检测高电平的电平是否低于预定电平以调节控制信号的电平。