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公开(公告)号：US10923482B2
公开(公告)日：2021-02-16
申请号：US16396916
申请日：2019-04-29
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor： Germain Bossu , Nigel Chan
Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.
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公开(公告)号：US20240371879A1
公开(公告)日：2024-11-07
申请号：US18311935
申请日：2023-05-04
Applicant: GlobalFoundries U.S. Inc.
Inventor： Germain Bossu , Nigel Chan
Abstract: An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.
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