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    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    1.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20240282776A1

    公开(公告)日：2024-08-22

    申请号：US18653473

    申请日：2024-05-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    Semiconductor structure including sectioned well region
    2.
    发明授权
    Semiconductor structure including sectioned well region 有权

    公开(公告)号：US12046603B2

    公开(公告)日：2024-07-23

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    Eight-transistor static random access memory cell
    3.
    发明授权
    Eight-transistor static random access memory cell 有权

    公开(公告)号：US11488967B2

    公开(公告)日：2022-11-01

    申请号：US17211903

    申请日：2021-03-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jörg D. Schmid ,  Nigel Chan

    IPC: G11C11/417 ,  H01L27/11 ,  G11C11/412

    Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure. Various interconnects (including, but not limited to, silicide bridges and/or contact straps) provide the internal and electrical connections required for making the 8T SRAM cell operational and for incorporating the 8T SRAM cell into an array of such cells.

    IC product with a novel bit cell design and a memory array comprising such bit cells
    4.
    发明授权
    IC product with a novel bit cell design and a memory array comprising such bit cells 有权

    公开(公告)号：US10923482B2

    公开(公告)日：2021-02-16

    申请号：US16396916

    申请日：2019-04-29

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Germain Bossu ,  Nigel Chan

    IPC: H01L27/11 ,  H01L27/02 ,  H01L29/08

    Abstract: Disclosed is an illustrative bit cell that includes a first inverter circuit that includes a first input node and a first output node and a second inverter circuit that includes a second input node and a second output node, wherein the first output node is coupled to the second input node and the second output node is coupled to the first input node. The bit cell also includes a first extension field effect transistor that includes a first gate structure, a first cell-internal S/D region and a first cell boundary node S/D region, wherein first cell-internal S/D region electrically terminates within the cell boundary. The first gate structure is electrically coupled to one of the first or second input nodes and it is also shorted to the first cell-internal S/D region.

    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
    5.
    发明公开
    SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION 审中-公开

    公开(公告)号：US20230163134A1

    公开(公告)日：2023-05-25

    申请号：US17533402

    申请日：2021-11-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet Jain ,  Nigel Chan ,  Mahbub Rashed

    IPC: H01L27/12

    CPC classification number: H01L27/1207

    Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P− silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

    IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME
    6.
    发明申请
    IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20240371879A1

    公开(公告)日：2024-11-07

    申请号：US18311935

    申请日：2023-05-04

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Germain Bossu ,  Nigel Chan

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/94

    Abstract: An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.

    EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL
    8.
    发明申请
    EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL 有权

    公开(公告)号：US20220310629A1

    公开(公告)日：2022-09-29

    申请号：US17211903

    申请日：2021-03-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jörg D. Schmid ,  Nigel Chan

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417

    Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure. Various interconnects (including, but not limited to, silicide bridges and/or contact straps) provide the internal and electrical connections required for making the 8T SRAM cell operational and for incorporating the 8T SRAM cell into an array of such cells.

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