公开(公告)号：US20230361127A1

公开(公告)日：2023-11-09

申请号：US18139981

申请日：2023-04-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

公开(公告)号：US20230059665A1

公开(公告)日：2023-02-23

申请号：US17407680

申请日：2021-08-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

公开(公告)号：US11784189B2

公开(公告)日：2023-10-10

申请号：US17407680

申请日：2021-08-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.