公开(公告)号：US20240273275A1

公开(公告)日：2024-08-15

申请号：US18169315

申请日：2023-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Manubhai Patel Jignesh ,  James A. Culp ,  Bradley A. Orner ,  Haritez Narisetty

IPC: G06F30/392 ,  G06F30/31

CPC classification number: G06F30/392 ,  G06F30/31 ,  G06F2111/20

Abstract: Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).