公开(公告)号：US20240273275A1

公开(公告)日：2024-08-15

申请号：US18169315

申请日：2023-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Manubhai Patel Jignesh ,  James A. Culp ,  Bradley A. Orner ,  Haritez Narisetty

IPC: G06F30/392 ,  G06F30/31

CPC classification number: G06F30/392 ,  G06F30/31 ,  G06F2111/20

Abstract: Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).

公开(公告)号：US20240371809A1

公开(公告)日：2024-11-07

申请号：US18311712

申请日：2023-05-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haritez Narisetty ,  Manubhai Patel Jignesh ,  Ching Theng Lew ,  Ananth Sundaram ,  Muhammed Shafi Kunnathodi ,  Praveen Paul Arotha ,  Varuna AnanthaPadmanabha Baipadi

IPC: H01L23/00 ,  G06F30/39 ,  H01L23/544 ,  H01L25/065

Abstract: Embodiments of the disclosure provide a structure including a passive component traversing multiple semiconductor chips, with related systems and methods. A structure of the disclosure includes a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface. A passive component traverses the interface between the first chip and the second chip of the plurality of stacked semiconductor chips. The passive component includes a first portion within the first chip and a second portion within the second chip.