公开(公告)号：US11218137B2

公开(公告)日：2022-01-04

申请号：US16847807

申请日：2020-04-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uttam Saha ,  Mahbub Rashed

IPC: H03K3/037 ,  H03K19/20

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.

公开(公告)号：US11050414B1

公开(公告)日：2021-06-29

申请号：US16881053

申请日：2020-05-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uttam Saha ,  Mahbub Rashed

IPC: H03K3/037 ,  H03K19/20

Abstract: A dynamic single input-dual output latch includes input, feedback, and output stages. In the input stage, operations are dependent on a clock signal (CLK) and a feedback signal (FB) from the feedback stage. For example, when FB is at a low voltage level and CLK switches to a high voltage level, the input stage enters a data capture mode. Once data has been captured, FB switches back to the high voltage level, placing the input stage in a data hold mode. In the output stage, operations are dependent on CLK but independent of FB. For example, instead of initiating output signal stabilization only after both CLK and FB are at high voltage levels, weak pull-down transistors (including at least one CLK-controlled pull-down transistor) are employed in the output stage to ensure output signal stabilization is initiated after data capture has begun but before FB switches to the high voltage level.

公开(公告)号：US20250080091A1

公开(公告)日：2025-03-06

申请号：US18459522

申请日：2023-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain ,  Uttam Saha

IPC: H03K3/037 ,  H01L27/092

Abstract: A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.