公开(公告)号：US12183394B2

公开(公告)日：2024-12-31

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/419 ,  H03K3/356

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US12148702B2

公开(公告)日：2024-11-19

申请号：US17879574

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

公开(公告)号：US20240222356A1

公开(公告)日：2024-07-04

申请号：US18149279

申请日：2023-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Jia Zeng ,  Xuelian Zhu ,  Navneet K. Jain ,  Mahbub Rashed ,  Jacob Mazza

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

公开(公告)号：US11894845B1

公开(公告)日：2024-02-06

申请号：US17898937

申请日：2022-08-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H03K3/00 ,  H03K3/012 ,  H03K5/01 ,  H03K3/037 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00013

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

公开(公告)号：US20230326520A1

公开(公告)日：2023-10-12

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H03K3/356

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356078 ,  H03K3/356026

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230282707A1

公开(公告)日：2023-09-07

申请号：US17687941

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L27/1203 ,  H01L29/7838

Abstract: Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.

公开(公告)号：US11322200B1

公开(公告)日：2022-05-03

申请号：US17120325

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

公开(公告)号：US11218137B2

公开(公告)日：2022-01-04

申请号：US16847807

申请日：2020-04-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uttam Saha ,  Mahbub Rashed

IPC: H03K3/037 ,  H03K19/20

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.

公开(公告)号：US11050414B1

公开(公告)日：2021-06-29

申请号：US16881053

申请日：2020-05-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uttam Saha ,  Mahbub Rashed

IPC: H03K3/037 ,  H03K19/20

Abstract: A dynamic single input-dual output latch includes input, feedback, and output stages. In the input stage, operations are dependent on a clock signal (CLK) and a feedback signal (FB) from the feedback stage. For example, when FB is at a low voltage level and CLK switches to a high voltage level, the input stage enters a data capture mode. Once data has been captured, FB switches back to the high voltage level, placing the input stage in a data hold mode. In the output stage, operations are dependent on CLK but independent of FB. For example, instead of initiating output signal stabilization only after both CLK and FB are at high voltage levels, weak pull-down transistors (including at least one CLK-controlled pull-down transistor) are employed in the output stage to ensure output signal stabilization is initiated after data capture has begun but before FB switches to the high voltage level.

公开(公告)号：US12288782B2

公开(公告)日：2025-04-29

申请号：US17679655

申请日：2022-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Juhan Kim ,  Sangmoon J. Kim ,  Mahbub Rashed ,  Navneet K. Jain

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.