公开(公告)号：US11621035B1

公开(公告)日：2023-04-04

申请号：US17447841

申请日：2021-09-16

申请人： GlobalFoundries U.S. Inc.

发明人： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC分类号： G11C8/10 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08 ,  G11C7/10

摘要： Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.

公开(公告)号：US20230082931A1

公开(公告)日：2023-03-16

申请号：US17447841

申请日：2021-09-16

申请人： GlobalFoundries U.S. Inc.

发明人： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC分类号： G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

摘要： Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.