公开(公告)号：US20240046983A1

公开(公告)日：2024-02-08

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  H03K3/356 ,  G11C11/412

CPC classification number: G11C11/419 ,  H03K3/356026 ,  H03K3/356078 ,  G11C11/412

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230082931A1

公开(公告)日：2023-03-16

申请号：US17447841

申请日：2021-09-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC: G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

Abstract: Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.

公开(公告)号：US11862240B2

公开(公告)日：2024-01-02

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C16/10 ,  G11C11/419 ,  H03K3/356 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356026 ,  H03K3/356078

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US11635958B1

公开(公告)日：2023-04-25

申请号：US17567209

申请日：2022-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Gregory A. Northrop ,  Shashank Nemawarkar ,  Shivraj Gurpadappa Dharne

IPC: G06F9/30 ,  G06F7/544

Abstract: Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.

公开(公告)号：US12183394B2

公开(公告)日：2024-12-31

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/419 ,  H03K3/356

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20230326520A1

公开(公告)日：2023-10-12

申请号：US17658189

申请日：2022-04-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/419 ,  G11C11/412 ,  H03K3/356

CPC classification number: G11C11/419 ,  G11C11/412 ,  H03K3/356078 ,  H03K3/356026

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US11621035B1

公开(公告)日：2023-04-04

申请号：US17447841

申请日：2021-09-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC: G11C8/10 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.