Liner assemblies for substrate processing systems

    公开(公告)号:US11668006B2

    公开(公告)日:2023-06-06

    申请号:US17162729

    申请日:2021-01-29

    摘要: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

    High resistivity SOI wafers and a method of manufacturing thereof

    公开(公告)号:US11081386B2

    公开(公告)日:2021-08-03

    申请号:US16948376

    申请日:2020-09-16

    摘要: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.

    METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR

    公开(公告)号:US20190273015A1

    公开(公告)日:2019-09-05

    申请号:US16409038

    申请日:2019-05-10

    摘要: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

    Liner assemblies for substrate processing systems

    公开(公告)号:US11345996B2

    公开(公告)日:2022-05-31

    申请号:US16235729

    申请日:2018-12-28

    摘要: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

    Liner assemblies for substrate processing systems

    公开(公告)号:US10907251B2

    公开(公告)日:2021-02-02

    申请号:US16235671

    申请日:2018-12-28

    摘要: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.

    HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF

    公开(公告)号:US20210005507A1

    公开(公告)日:2021-01-07

    申请号:US16948376

    申请日:2020-09-16

    IPC分类号: H01L21/762

    摘要: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.