公开(公告)号：US20040008730A1

公开(公告)日：2004-01-15

申请号：US10064445

申请日：2002-07-15

申请人： GlobespanVirata Incorporated

发明人： Amir Helzer

IPC分类号： H04J003/06

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data. Concurrently, the input sampling module can access the process information from the dual clock FIFO buffer using the skewed clock signal. Based at least in part on this process information, one or more process operations can be performed on the requested data. In other implementations, the storage and subsequent access of process information from a dual-clock FIFO is omitted. The present invention finds particular benefit in accessing data stored in synchronous memory, such as synchronous dynamic random access memory (SDRAM) and synchronous static random access memory (SSRAM).

摘要翻译： 本文提供了用于改进存储数据的同步访问的系统和方法。 数据请求者发送用于由数据源接收的时钟信号和读取请求信号，由于数据请求者和数据源之间的信号路径的延迟，接收到时钟信号和读取请求信号的偏移版本。 因此，数据请求者向其输入采样模块提供偏斜时钟和读取请求信号，以模拟信号路径的延迟。 此外，数据请求器将与请求的数据相关联的处理信息提供给双时钟先进先出（FIFO）缓冲器。 当输入采样模块使用偏斜的读取请求信号检测到读取请求时，输入采样模块可以使用该信号和偏斜时钟信号从数据源采样数据信号以获得所请求的数据。 同时，输入采样模块可以使用偏斜时钟信号从双时钟FIFO缓冲器访问过程信息。 至少部分地基于该处理信息，可以对所请求的数据执行一个或多个处理操作。 在其他实现中，省略了来自双时钟FIFO的处理信息的存储和后续访问。 本发明特别有利于存取存储在同步存储器中的数据，如同步动态随机存取存储器（SDRAM）和同步静态随机存取存储器（SSRAM）。