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    System and method for applying transmit windowing in ADSL+networks
    1.
    发明申请
    System and method for applying transmit windowing in ADSL+networks 有权
    在ADSL +网络中应用传输窗口的系统和方法

    公开(公告)号：US20030235150A1

    公开(公告)日：2003-12-25

    申请号：US10250236

    申请日：2003-06-16

    申请人： GLOBESPANVIRATA INCORPORATED

    发明人： Albert Rapaport

    IPC分类号： H04J011/00 ,  H04B003/20

    CPC分类号： H04L27/2605

    摘要： A system and method for formatting and transmitting DMT symbols. For each symbol to be transmitted, the last Lcp samples of the symbol are prepended to the symbol as a cyclic prefix. Next, of the samples contained within the cyclic prefix, the first null2 samples are appended to the symbol as a cyclic suffix. By providing the above described cyclic prefix and suffix, sharp PSD transitions are provided in the first overlapped RFI band (1.8-2 MHz) and out of band PSD. Upon formatting, each symbol is transmitted so that its transmission overlaps the prior symbol by null2 samples. This results in the output signal being shaped by a raised cosine function for the duration of the null2 overlap.

    摘要翻译： 用于格式化和发送DMT符号的系统和方法。 对于要发送的每个符号，符号的最后一个Lcp样本作为循环前缀添加到符号。 接下来，循环前缀中包含的样本中，第一个Î2样本作为循环后缀附加到符号。 通过提供上述循环前缀和后缀，在第一重叠RFI频带（1.8-2MHz）和带外PSD中提供了尖锐的PSD转换。 在格式化时，每个符号被传输，使得其传输与先前的符号重叠，由2θ的样本。 这导致在α2重叠的持续时间内，输出信号由升余弦函数整形。

    INTEGRATED CIRCUIT CAPABLE OF OPERATING IN MULTIPLE ORIENTATIONS
    2.
    发明申请
    INTEGRATED CIRCUIT CAPABLE OF OPERATING IN MULTIPLE ORIENTATIONS 有权
    集成电路可在多个方位运行

    公开(公告)号：US20030176013A1

    公开(公告)日：2003-09-18

    申请号：US10063036

    申请日：2002-03-13

    申请人： GlobespanVirata Incorporated

    发明人： David Stuart Baker

    IPC分类号： H01L021/44 ,  H01L023/48

    CPC分类号： H05K3/303 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/029 ,  H05K1/0295 ,  H05K3/306 ,  H05K2201/09954 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49139 ,  Y10T29/49169 ,  Y10T29/49208 ,  H01L2924/00

    摘要： An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

    摘要翻译： 提供能够以多个插入方向操作的集成电路设计。 具体地，本发明的电路设计包括集成电路封装，其具有从集成电路封装延伸并且对称地布置的多个接触元件，以使集成电路能够以至少两个离散取向插入电路板上。 多个接触元件被指定为定位销，所述定向销布置成使得在集成电路封装上电时，定向销将指示集成电路封装在电路板中的插入取向的取向信号传送。 提供多个多路复用器装置用于响应于来自定向销的取向信号在接触元件和集成电路功能电路之间路由信号。

    System and method for determining fault path behavior
    3.
    发明申请
    System and method for determining fault path behavior 失效

    公开(公告)号：US20030126505A1

    公开(公告)日：2003-07-03

    申请号：US09683752

    申请日：2002-02-11

    申请人： GlobespanVirata Incorporated

    发明人： Herbert Lyvirn Lacey III

    IPC分类号： G06F011/26

    CPC分类号： G06F11/3672

    摘要： A system and method for determining fault path behavior in a computer software system. An error or event, the occurrence of which is to be tested, is assigned a probability value and an array of elements populated by pseudo-random numbers. Upon each operation of the system under test the current array value is compared against the probability value. If the current array value is greater than or equal than the probability value, the error or event is simulated within the software. Otherwise, the event is not simulated and the software is left to operate conventionally. The array is incremented upon each occurrence of the system under test.

    System and method for improved synchronous data access
    4.
    发明申请
    System and method for improved synchronous data access 有权
    用于改进同步数据访问的系统和方法

    公开(公告)号：US20040008730A1

    公开(公告)日：2004-01-15

    申请号：US10064445

    申请日：2002-07-15

    申请人： GlobespanVirata Incorporated

    发明人： Amir Helzer

    IPC分类号： H04J003/06

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

    摘要： A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data. Concurrently, the input sampling module can access the process information from the dual clock FIFO buffer using the skewed clock signal. Based at least in part on this process information, one or more process operations can be performed on the requested data. In other implementations, the storage and subsequent access of process information from a dual-clock FIFO is omitted. The present invention finds particular benefit in accessing data stored in synchronous memory, such as synchronous dynamic random access memory (SDRAM) and synchronous static random access memory (SSRAM).

    摘要翻译： 本文提供了用于改进存储数据的同步访问的系统和方法。 数据请求者发送用于由数据源接收的时钟信号和读取请求信号，由于数据请求者和数据源之间的信号路径的延迟，接收到时钟信号和读取请求信号的偏移版本。 因此，数据请求者向其输入采样模块提供偏斜时钟和读取请求信号，以模拟信号路径的延迟。 此外，数据请求器将与请求的数据相关联的处理信息提供给双时钟先进先出（FIFO）缓冲器。 当输入采样模块使用偏斜的读取请求信号检测到读取请求时，输入采样模块可以使用该信号和偏斜时钟信号从数据源采样数据信号以获得所请求的数据。 同时，输入采样模块可以使用偏斜时钟信号从双时钟FIFO缓冲器访问过程信息。 至少部分地基于该处理信息，可以对所请求的数据执行一个或多个处理操作。 在其他实现中，省略了来自双时钟FIFO的处理信息的存储和后续访问。 本发明特别有利于存取存储在同步存储器中的数据，如同步动态随机存取存储器（SDRAM）和同步静态随机存取存储器（SSRAM）。

    Communications system using rings architecture
    6.
    发明申请
    Communications system using rings architecture 审中-公开
    通信系统采用环形架构

    公开(公告)号：US20030191861A1

    公开(公告)日：2003-10-09

    申请号：US10064329

    申请日：2002-07-02

    申请人： GlobespanVirata Incorporated

    发明人： Ilia Greenblat

    IPC分类号： G06F015/16

    CPC分类号： H04L49/25 ,  G06F15/78 ,  G06F15/7825 ,  H04L12/42 ,  H04L12/422 ,  H04L12/427 ,  H04L12/433 ,  H04L12/437 ,  H04L12/4625 ,  H04L12/4637 ,  H04L12/5601 ,  H04L45/04 ,  H04L45/18 ,  H04L45/22 ,  H04L45/302 ,  H04L45/306 ,  H04L45/50 ,  H04L49/102 ,  H04L49/1553 ,  H04L49/30 ,  H04L49/3063 ,  H04L49/3081 ,  H04L49/40 ,  H04L69/12 ,  H04L2012/5612 ,  H04L2012/5618 ,  H04L2012/5627 ,  H04L2012/5638 ,  H04L2012/5656 ,  H04L2012/5665 ,  H04W28/06 ,  H04W40/00 ,  H04W80/00 ,  H04W84/00 ,  Y02D10/12 ,  Y02D10/13

    摘要： Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture. Additional inventive elements conveyed include: an architectural overview of a communications processor; a data path protocol support model for a communications processor; an exemplary network processor employed as the core packet processor for the communications processor; an exemplary rings-based SOC switch fabric architecture; and a variety of quality of support features.

    摘要翻译： 提供的系统和方法用于实现：用于通信和数据处理系统的环结构; 用于自动配置环形拓扑的枚举过程; 通过桥梁自动路由消息; 将环形拓扑扩展到外部设备; 提前预知功能，以提高效率; 等待重置操作恢复; 通过环形拓扑进行体内扫描; 交错排列; 和流浪消息检测和根除。 所传送的其他创造性元素包括：分组处理器的架构概述; 用于分组处理器的编程模型; 用于分组处理器的指令流水线; 并使用分组处理器作为基于环的体系结构的模块。 传达的附加创造性元素包括：通信处理器的架构概述; 用于通信处理器的数据路径协议支持模型; 用作通信处理器的核心分组处理器的示例性网络处理器; 一种示例性的基于环的SOC交换机架构; 和各种质量的支持功能。

    System and method for scheduling transmit messages using credit-based flow control
    7.
    发明申请
    System and method for scheduling transmit messages using credit-based flow control 审中-公开
    使用基于信用的流量控制来调度传输消息的系统和方法

    公开(公告)号：US20030133463A1

    公开(公告)日：2003-07-17

    申请号：US09683770

    申请日：2002-02-12

    申请人： GlobespanVirata Incorporated

    发明人： Herbert Lyvirn Lacey III

    IPC分类号： H04L012/28

    CPC分类号： H04L47/10 ,  H04L47/286 ,  H04M11/062

    摘要： A system and method for facilitating the scheduling and transmission of transmit protocol messages. Initially, a write credit count is maintained indicating the number of write credits available to a transmit message processor. Upon receipt of a data frame for transmission to a data pump, the transmit message processor determines whether the write credit count is greater than 0. Of so, the frame is dequeued and the message is sent to the data pump for transmission on the wire to a receiving peer end. However, if the write credit count is 0, a waiting_for_write_credit flag is set to true indicating that the transmit processor has a frame waiting for transmission, but lacks sufficient write credits to send the frame to the data pump. Once an additional write credit is received from the data pump, the write credit count is incremented and the waiting_for_write_credit flag is checked to see if any frames are waiting to be send. If so, the transmit message processor is activated, resulting in the transmission of the waiting frame.

    摘要翻译： 一种用于促进传输协议消息的调度和传输的系统和方法。 最初，维持写入信用计数，指示发送消息处理器可用的写入信用的数量。 在接收到用于发送到数据泵的数据帧时，发送消息处理器确定写入信用计数是否大于0.因此，帧被列出并且消息被发送到数据泵以在线路上传输到 接收对端。 然而，如果写入信用计数为0，则wait_for_write_credit标志被设置为true，表示发送处理器具有等待传输的帧，但是缺少足够的写入信用以将帧发送到数据泵。 一旦从数据泵接收到额外的写入信用额度，写入信用计数将被递增，并且等待_写入_信号标志被检查以查看是否有任何帧正在等待发送。 如果是这样，则发送消息处理器被激活，导致等待帧的发送。

    System and method for improved data protection in PONs
    8.
    发明申请
    System and method for improved data protection in PONs 有权
    PON改进数据保护的系统和方法

    公开(公告)号：US20040136534A1

    公开(公告)日：2004-07-15

    申请号：US10340651

    申请日：2003-01-13

    申请人： GlobespanVirata Incorporated

    发明人： James Stiscia ,  Raymond Chen

    IPC分类号： H04K001/00

    CPC分类号： H04L63/0428

    摘要： Mechanisms for providing a subscriber-side interface with a passive optical network are described herein. An optical network termination (ONT) having an integrated broadband passive optical network processor is utilized to receive downstream data from an optical line termination (OLT) via a passive optical network and provide the contents of the downstream data to one or more subscriber devices via one or more data interfaces. Similarly, the ONT is adapted to receive and transmit upstream data from the one or more subscriber devices to the OLT via the passive optical network. The ONT preferably implements one or more encryption/decryption mechanisms, such as the digital encryption standard (DES), to provide data protection in addition to, or in place of, data churning provided for by the ITU G.983 recommendations.

    摘要翻译： 本文描述了提供与无源光网络的用户侧接口的机制。 利用具有集成宽带无源光网络处理器的光网络终端（ONT），经由无源光网络从光线路终端（OLT）接收下行数据，并通过一个或多个用户设备将下游数据的内容提供给一个或多个用户设备 或更多的数据接口。 类似地，ONT适于经由无源光网络从一个或多个订户设备接收和发送上行数据到OLT。 ONT优选地实现一个或多个加密/解密机制，例如数字加密标准（DES），除了由ITU G.983建议提供的数据转换之外或代替ITU G.983建议提供的数据转换提供数据保护。

    Intelligent PPPOE initialization
    9.
    发明申请
    Intelligent PPPOE initialization 审中-公开
    智能PPPOE初始化

    公开(公告)号：US20040071133A1

    公开(公告)日：2004-04-15

    申请号：US10065393

    申请日：2002-10-11

    申请人： GlobespanVirata Incorporated

    发明人： Jon A. Yusko ,  Kraig E. Haglund

    IPC分类号： H04L012/66

    CPC分类号： H04L12/2859 ,  H04L12/2856 ,  H04L12/2885

    摘要： An exemplary mechanism for intelligent Point-to-Point Protocol over Ethernet (PPPoE) initialization is disclosed herein. During the PPPoE discovery stage, a PPPoE client of a CPE determines the status of a connection between the CPE and an access concentrator prior to transmitting a PADI and/or PADR packet. If a physical layer connection is established, the PPPoE client can provide the packet to the physical interface for transmission to the access concentrator. If a physical layer connection is not established, the PPPoE client either periodically rechecks the status of the connection until a physical layer connection is established or the PPPoE can terminate the PPPoE discovery stage after a certain number of iterations. Additionally, prior to waiting for a PADO or PADS packet, the PPPoE client can be adapted to check the status of the connection. If a physical layer connection exists, the PPPoE client can initiate the wait for the packet. However, if a physical layer connection has not been established, the PPPoE client can either reattempt a previous step of the PPPoE discovery stage or terminate the PPPoE discovery stage.

    摘要翻译： 本文公开了用于以太网智能点对点协议（PPPoE）初始化的示例性机制。 在PPPoE发现阶段，在发送PADI和/或PADR分组之前，CPE的PPPoE客户端确定CPE与接入集中器之间的连接的状态。 如果建立了物理层连接，则PPPoE客户端可以将数据包提供给物理接口，以传输到接入集中器。 如果没有建立物理层连接，PPPoE客户端定期重新检查连接的状态，直到建立物理层连接，或PPPoE可以在一定次数的迭代后终止PPPoE发现阶段。 此外，在等待PADO或PADS数据包之前，可以对PPPoE客户端进行调整，以检查连接的状态。 如果存在物理层连接，则PPPoE客户端可以启动等待数据包。 然而，如果物理层连接尚未建立，则PPPoE客户端可以重新尝试先前的PPPoE发现阶段，或者终止PPPoE发现阶段。