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公开(公告)号：US10103431B2
公开(公告)日：2018-10-16
申请号：US15135408
申请日：2016-04-21
Applicant: Google Inc.
Inventor： Paul Swirhun , Arnold Feldman
Abstract: A method including identifying clusters of antenna elements of a phased array antenna. For each cluster of antenna elements, the method includes identifying a reference antenna element of the cluster of antenna elements and identifying pairs of calibration antenna elements of the cluster of antenna elements. For each pair of calibration antenna elements, the method includes executing a calibration routine configured to determine a calibration adjustment for each antenna element of the pair of calibration antenna elements based on the reference antenna element. The method also includes determining a leveling adjustment for each antenna element of the phased array antenna. The method further includes adjusting the element gain and the element phase of each antenna element of the phased array antenna based on the corresponding leveling adjustment to equalize a transmission gain and a transmission phase of each signal path of the phased array antenna.
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公开(公告)号：US20180090851A1
公开(公告)日：2018-03-29
申请号：US15277149
申请日：2016-09-27
Applicant: Google Inc.
Inventor： Arnold Feldman , Leesa Marle Noujelm , Michael J. Buckley
CPC classification number: H01Q21/065 , H01Q1/12 , H01Q1/42 , H01Q1/48 , H01Q5/20 , H01Q9/0407 , H01Q15/008 , H01Q21/0075 , H01Q21/0087 , H01Q21/24
Abstract: A phased-array antenna includes an antenna layer of a stacked printed circuit board, a ground plane layer of the stacked printed circuit board spaced apart from the antenna layer, and a first dielectric layer of the stacked printed circuit board disposed between and in opposed contact with the antenna layer and the ground plane layer. The antenna layer includes an associated metal patch pattern defined by a series of slots. The stacked printed circuit board defines a thickness extending between a top end of the stacked printed circuit board and a bottom end of the stacked printed circuit board. The phased-array antenna includes a series of ground vias extending between the top and bottom ends of the stacked printed circuit board. The ground vias are configured to suppress surface waves propagating across the stacked printed circuit board.
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公开(公告)号：US09871602B2
公开(公告)日：2018-01-16
申请号：US15244241
申请日：2016-08-23
Applicant: Google Inc.
Inventor： Arnold Feldman , Benjamin Joseph Mossawir
IPC: H04B3/46 , H04B17/30 , H03G3/00 , H03G3/20 , H03G3/30 , H01Q3/26 , H01Q3/34 , H04B17/14 , H03G1/00 , H03K5/1532
CPC classification number: H04B17/30 , H01Q3/267 , H01Q3/34 , H03G1/0017 , H03G3/00 , H03G3/20 , H03G3/301 , H03K5/1532 , H04B17/14
Abstract: A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.
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公开(公告)号：US20170041087A1
公开(公告)日：2017-02-09
申请号：US15244241
申请日：2016-08-23
Applicant: Google Inc.
Inventor： Arnold Feldman , Benjamin Joseph Mossawir
IPC: H04B17/30 , H03K5/1532 , H03G1/00
CPC classification number: H04B17/30 , H01Q3/267 , H01Q3/34 , H03G1/0017 , H03G3/00 , H03G3/20 , H03G3/301 , H03K5/1532 , H04B17/14
Abstract: A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.
Abstract translation: 一种用于操作移相器芯片RF自检的方法。 该方法包括通过控制硬件将来自相位锁定环路的第一信号输出到前置放大器和输入峰值检测器，由控制硬件将来自前置放大器的第二信号输出到被测器件，选择 控制硬件，目标电平，并通过控制硬件调整前置放大器的前置放大器增益，使输入峰值检测器值近似匹配目标电平。 输入峰值检测器被配置为基于第一信号输出输入峰值检测器值。
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公开(公告)号：US09171642B2
公开(公告)日：2015-10-27
申请号：US14285660
申请日：2014-05-23
Applicant: Google Inc.
Inventor： Lynn Bos , Arnold Feldman , Shahriar Rabii
CPC classification number: G11C27/028 , G11C27/02 , G11C27/024
Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.
Abstract translation: 具有采样网络的电路可以包括一对电容器，其中每个电容器具有第一节点和第二节点; 第一对开关，其将相应的差分输入电压信号通信耦合到每个电容器的第一节点; 以及第二对开关，其将每个电容器的第二节点通信地耦合到共模电压源。 每个电容器的第二节点处的对应差分输出电压信号可以使用差分开关通信耦合。 第二对开关可以与差动开关并联。 差分开关的时钟信号可以在对于第二对开关中的每一个的对应时钟信号解除置位之前被解除断言。
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Patent Agency Ranking
公开(公告)号：US09231525B2
公开(公告)日：2016-01-05
申请号：US14192964
申请日：2014-02-28
Applicant: Google Inc.
Inventor： Arnold Feldman
CPC classification number: H03F1/0205 , G05F1/575 , H03F3/45071 , H03F2200/471 , H03F2203/45034
Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.
Abstract translation: 公开了一种用于配置包括两级放大器的电路的系统和技术，该电路包括至少包含一个差分放大器的第一级，至少包含一个晶体管的第二级，以及被配置为向补偿组件提供栅极电压的感测电路。 补偿分量可以被配置为连接第一级和第二级并产生超前滞后补偿。 补偿部件可以包含补偿电容器和与补偿电容器串联连接的可变补偿电阻部件。
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公开(公告)号：US20150249430A1
公开(公告)日：2015-09-03
申请号：US14192964
申请日：2014-02-28
Applicant: Google Inc.
Inventor： Arnold Feldman
CPC classification number: H03F1/0205 , G05F1/575 , H03F3/45071 , H03F2200/471 , H03F2203/45034
Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.
Abstract translation: 公开了一种用于配置包括两级放大器的电路的系统和技术，该电路包括至少包含一个差分放大器的第一级，至少包含一个晶体管的第二级，以及被配置为向补偿组件提供栅极电压的感测电路。 补偿分量可以被配置为连接第一级和第二级并产生超前滞后补偿。 补偿部件可以包含补偿电容器和与补偿电容器串联连接的可变补偿电阻部件。
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公开(公告)号：US09882601B1
公开(公告)日：2018-01-30
申请号：US14526000
申请日：2014-10-28
Applicant: Google Inc.
Inventor： Arnold Feldman
IPC: H04B1/44
CPC classification number: H04B1/44
Abstract: A circuit includes a power amplifier that includes a transformer having a primary winding and a secondary winding. The secondary winding has a first terminal and a second terminal. The circuit also includes a transmit/receive switch electrically connected between the first terminal of the secondary winding and electrical ground. The second terminal of the secondary winding is electrically connected to an antenna that transmits signals based on an output of the power amplifier and to an input of a second amplifier that is also connected to the antenna. The transmit/receive switch selectively switches between a closed position that connects the secondary winding to ground in a transmit mode and an open position that disconnects the secondary winding from ground in a receive mode.
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公开(公告)号：US20170310004A1
公开(公告)日：2017-10-26
申请号：US15135408
申请日：2016-04-21
Applicant: Google Inc.
Inventor： Paul Swirhun , Arnold Feldman
Abstract: A method including identifying clusters of antenna elements of a phased array antenna. For each cluster of antenna elements, the method includes identifying a reference antenna element of the cluster of antenna elements and identifying pairs of calibration antenna elements of the cluster of antenna elements. For each pair of calibration antenna elements, the method includes executing a calibration routine configured to determine a calibration adjustment for each antenna element of the pair of calibration antenna elements based on the reference antenna element. The method also includes determining a leveling adjustment for each antenna element of the phased array antenna. The method further includes adjusting the element gain and the element phase of each antenna element of the phased array antenna based on the corresponding leveling adjustment to equalize a transmission gain and a transmission phase of each signal path of the phased array antenna.
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公开(公告)号：US20140253177A1
公开(公告)日：2014-09-11
申请号：US14285660
申请日：2014-05-23
Applicant: Google Inc.
Inventor： Lynn Bos , Arnold Feldman , Shahriar Rabii
IPC: G11C27/02
CPC classification number: G11C27/028 , G11C27/02 , G11C27/024
Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.
Abstract translation: 具有采样网络的电路可以包括一对电容器，其中每个电容器具有第一节点和第二节点; 第一对开关，其将相应的差分输入电压信号通信耦合到每个电容器的第一节点; 以及第二对开关，其将每个电容器的第二节点通信地耦合到共模电压源。 每个电容器的第二节点处的对应差分输出电压信号可以使用差分开关通信耦合。 第二对开关可以与差动开关并联。 差分开关的时钟信号可以在对于第二对开关中的每一个的对应时钟信号解除置位之前被解除断言。
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