公开(公告)号：US20170103315A1

公开(公告)日：2017-04-13

申请号：US15389288

申请日：2016-12-22

申请人： Google Inc.

发明人： Gregory Michael Thorson ,  Christopher Aaron Clark ,  Dan Luu

IPC分类号： G06N3/08 ,  G06N5/04

CPC分类号： G06N3/08 ,  G06N3/063 ,  G06N5/04

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

公开(公告)号：US20180260220A1

公开(公告)日：2018-09-13

申请号：US15454214

申请日：2017-03-09

申请人： Google Inc.

发明人： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC分类号： G06F9/30 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58

CPC分类号： G06F9/3001 ,  G06F7/588 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8046 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06N3/063

摘要： A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20160342889A1

公开(公告)日：2016-11-24

申请号：US14845117

申请日：2015-09-03

申请人： Google Inc.

发明人： Gregory Michael Thorson ,  Christopher Aaron Clark ,  Dan Luu

IPC分类号： G06N3/04

CPC分类号： G06N3/08 ,  G06N3/063 ,  G06N5/04

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

摘要翻译： 一种用于对包括多个层的神经网络执行神经网络计算的电路，所述电路包括：激活电路，被配置为接收累积值的向量并且被配置为对每个累积值应用函数以生成激活值的向量; 以及归一化电路，其耦合到所述激活电路并且被配置为从每个激活值生成相应的归一化值。