公开(公告)号：US09875104B2

公开(公告)日：2018-01-23

申请号：US15014265

申请日：2016-02-03

申请人： Google Inc.

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/302 ,  G06F7/52 ,  G06F9/355 ,  G06F9/30 ,  G06F17/16 ,  G06F9/32

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US09875100B2

公开(公告)日：2018-01-23

申请号：US15456812

申请日：2017-03-13

申请人： Google Inc.

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/302 ,  G06F7/52 ,  G06F9/30 ,  G06F17/16 ,  G06F9/32 ,  G06F9/355

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20170220352A1

公开(公告)日：2017-08-03

申请号：US15014265

申请日：2016-02-03

申请人： Google Inc.

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/355 ,  G06F9/30

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20170220345A1

公开(公告)日：2017-08-03

申请号：US15456812

申请日：2017-03-13

申请人： Google Inc.

发明人： Dong Hyuk Woo ,  Andrew Everett Phelps

IPC分类号： G06F9/30

CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US20170103313A1

公开(公告)日：2017-04-13

申请号：US15389202

申请日：2016-12-22

申请人： Google Inc.

发明人： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC分类号： G06N3/08 ,  G06N5/04

CPC分类号： G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US09747546B2

公开(公告)日：2017-08-29

申请号：US14844524

申请日：2015-09-03

申请人： Google Inc.

发明人： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC分类号： G06N3/06 ,  G06N3/063 ,  G06F15/80

CPC分类号： G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20180260220A1

公开(公告)日：2018-09-13

申请号：US15454214

申请日：2017-03-09

申请人： Google Inc.

发明人： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC分类号： G06F9/30 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58

CPC分类号： G06F9/3001 ,  G06F7/588 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8046 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06N3/063

摘要： A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US09916279B1

公开(公告)日：2018-03-13

申请号：US14987443

申请日：2016-01-04

申请人： Google Inc.

发明人： Kyle Nesbit ,  Andrew Everett Phelps

IPC分类号： G06F15/173 ,  G06F3/06

CPC分类号： G06F15/17331 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067

摘要： A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

公开(公告)号：US20180046907A1

公开(公告)日：2018-02-15

申请号：US15686615

申请日：2017-08-25

申请人： Google Inc.

发明人： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC分类号： G06N3/063 ,  G06F15/80

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US09710748B2

公开(公告)日：2017-07-18

申请号：US15389202

申请日：2016-12-22

申请人： Google Inc.

发明人： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC分类号： G06N3/08 ,  G06N5/04

CPC分类号： G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

摘要： A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.