公开(公告)号：US11552197B2

公开(公告)日：2023-01-10

申请号：US16740089

申请日：2020-01-10

Applicant: Google LLC

Inventor： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/41 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  B82Y40/00

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US20230111689A1

公开(公告)日：2023-04-13

申请号：US18081177

申请日：2022-12-14

Applicant: Google LLC

Inventor： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L21/268 ,  H01L29/78

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

公开(公告)号：US12125916B2

公开(公告)日：2024-10-22

申请号：US18081177

申请日：2022-12-14

Applicant: Google LLC

Inventor： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L21/268 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y40/00

CPC classification number: H01L29/78618 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696 ,  B82Y40/00 ,  H01L29/7839

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.